Papers by Keyword: Bipolar Power Devices

Abstract: An optimized termination extension tutorial is reported for a small area (≈ 1mm² ) 4H-SiC NPN BJT. The extension system is based on a parametric JTE with isolation rings. Additional aspects such as (1) MESA angle, (2) relieving electric field on the base-drift junction, and (3) blocking the electric field from reaching border structure are investigated. A breakdown voltage greater than 10 kV is recorded, when drift region is n-doped to 8x10¹⁴ cm-3.

Abstract: The development of 4H-SiC PiN diodes capable of blocking to greater than 10 kV while having current ratings of 20 A at 100 A/cm2 is continuing in earnest. VF instability of these diodes continues to be a roadblock, but progress is being made, and a 20 A/10 kV 4H-SiC PiN diode wafer with an overall device yield of 40% has been fabricated. The latest device characteristics are discussed, along with details of approaches in improving the reverse recovery characteristics of these diodes to satisfy the requirements needed for implementation into high voltage inverter modules capable of switching at up to 20 kHz.

Abstract: A non-destructive technique to image the dislocations and other extended defects in SiC epitaxial layers has been developed. Basal plane dislocations (BPDs) and threading dislocations (TDs) are imaged. Photoluminescence from the dislocations is excited with the 364 and/or 351 nm lines of an argon ion laser and near-infrared light is collected. A computer controlled probe station takes multiple images and the mm-sized images are stitched together to form whole-wafer maps. The technique is applied to a set of four n+ wafers from the same boule with 50 um n- epitaxial layers. The epitaxy was grown with Cree’s low-BPD process. BPDs form as either single, isolated dislocations or as clusters encircling micropipes. The concentration of TDs is on the order 104/cm2 and the local concentration varies more than an order of magnitude. The advantages of mapping dislocations by UV-PL imaging compared to other techniques are discussed.

Abstract: We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a semi-sacrificial basal plane dislocation (BPD) conversion epilayer, polishing away a portion of that conversion epilayer to recover a smooth surface and then growing the device epilayers following specific methods to prevent the reintroduction of BPDs. With our best processing, we achieve a BPD density of < 10 cm-2 and an extended defect density of < 1.5 cm-2. Specifics of low BPD processing and particular concerns and metrics will be discussed in regard to process optimization and simplification.

Abstract: Forward voltage (VF) drift, in which a 4H-SiC PiN diode suffers from an irreversible increase in VF under forward current flow, continues to inhibit commercialization of 4H-SiC PiN diodes. We present our latest efforts at fabricating high blocking voltage (6 kV), high current (up to 50 A) 4H-SiC PiN diodes with the best combination of reverse leakage current (IR), forward voltage at rated current (VF), and VF drift yields. We have achieved greater than 60% total die yield onwafer for 50 A diodes with a chip size greater than 0.7 cm2. A comparison of the temperature dependent conduction and switching characteristics between a 50 A/6 kV 4H-SiC PiN diode and a commercially available 60 A/4.5 kV Si PiN diode is also presented.

Abstract: The PiN diode is an attractive device to exploit the high power material advantages of 4H-SiC. The combination of high critical field and adequate minority carrier lifetime has enabled devices that block up to 20 kV and carry 25 A. Furthermore, these devices exhibit fast switching with less reverse recovery charge than commercially available Si PiN diodes. The path to commercialization of the 4H-SiC PiN diode technology, however, has been hampered by a fundamental problem with the forward voltage stability resulting from stacking fault growth emanating from basal plane screw dislocations (BPD). In this contribution, we highlight the progress toward producing stable high power devices with sufficient yield to promote commercial interest. Two independent processes, LBPD1 and LBPD2, have been shown to be effective in reducing the BPD density and enhancing the forward voltage stability while being compatible with conventional power device fabrication. Applying the LBPD1 and LBPD2 processes to 10 kV (20 A and 50 A) 4H-SiC PiN diode technology has resulted in a dramatic improvement in the total device yield (forward, reverse, and forward drift yields) from 0% to >20%. The LBPD1 process appears to be more robust in terms of long term forward voltage stability.

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.