Papers by Keyword: Blocking Voltage

Abstract: An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO₂, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O₂ between amorphous SiO₂ and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in V_F over the 1300°C oxidized devices, without any impact on blocking characteristics.

Abstract: The multiple-zone junction termination extension (MJTE) is a widely used SiC edge termination technique that reduces sensitivity to implantation dose variations. It is typically implemented in multiple lithography and implantation events. To reduce process complexity, cycle time, and cost, a single photolithography/implantation (P/I) MJTE technique was developed and diodes with 3-zone and 120-zone JTEs were fabricated on the same wafer. Here, the process tolerance of the single (P/I) MJTE technique is evaluated by performing CCD monitored blocking voltage measurements on diodes from the same wafer with the 3-zone and 120-zone single (P/I) JTE. The 3-zone JTE diodes exhibited catastrophic localized avalanches at the interface between the 2nd and 3rd zones due to abrupt zone transitions. Diodes with the smooth transitioning 120-zone JTE exhibited no CCD detectable avalanches in their JTE regions up to the testing limit of 12 kV. Under thick dielectric (deposited for on-wafer diode interconnection), diodes with the single P/I 3-zone JTE failed due to significant loss of high-voltage capability, while their 120-zone JTE diode counterparts were minimally affected. Overall, the single (P/I) 120-zone JTE provides a process-tolerant and robust single P/I edge termination at no additional fabrication labor.

Abstract: The steady state characteristics of a normally-off 4H-SiC Bipolar Mode FET (BMFET) with a low on-resistance are investigated in a wide range of currents and temperatures by means of an intensive numerical simulation study which clarifies what are the main design constraints. Specific physical models and parameters strictly related to the presently available 4H-SiC technology are carefully taken into account. A drain forward current density up to 500 A/cm², a specific on-resistance lower than 2 mΩ∙cm² and a current gain in the order of a few tens are calculated. The blocking voltage is in excess of 1.3 kV with a low leakage current. These results are compared with the experimental data measured in the same test conditions of another SiC power device already introduced to the market.

Abstract: The multi-zone junction termination extension (MJTE) is a widely used edge termination technique for achieving high voltage SiC devices. It is commonly implemented with multiple lithography and implantation events. In order to reduce process complexity, cycle time, and cost, a single photolithography and single implant MJTE technique has been successfully developed. The method utilizes a pattern of finely graduated oxide windows that filter the implant dose and create a graded MJTE in a single implant and single photolithography step. Based on this technique, 6 kV / 0.09 cm2 PiN diodes were fabricated utilizing a 120-zone single-implant JTE design. This novel single-implant MJTE design captures 93% of the ideal breakdown voltage and has comparable performance and yield to a baseline three implant process.

Abstract: Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm^-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm^-1.

Abstract: A numerical simulation study focused on an oxide-free 4H-SiC power device that is based on a normally-off Bipolar Mode Field Effect Transistor (BMFET) structure, and therefore on the principle of conductivity modulation from minority carrier injection, is presented. Starting from a n-/n+ 4H-SiC epi-wafer, with an epitaxial layer thickness of a few microns, and considering the presently available 4H-SiC ion implantation technology, a completely planar SiC-based BMFET has been designed. Such a device has interesting features in terms of static forward and blocking I V characteristics for high power applications. The 4H-SiC fundamental physical models, such as the doping incomplete ionization and the carrier recombination processes, were taken into account during the simulations.

Abstract: Device size scaling of pseudo-vertical diamond Schottky barrier diodes (SBDs) has been characterized for high-power device applications based on the control of doping concentration and thickness of the p- CVD diamond layer. Decreasing parasitic resistance on the p+ layer utilizing lithography and etching makes possible to get a constant specific on-resistance of less than 20 mOhm-cm2 with increasing device size up to 200 µm. However, the leakage current under low reverse bias conditions is increased markedly. Due to the increase in the leakage current, the reverse operation limit is decreased from 2.4 to 1.3 MV/cm when the device size is increased from 30 to 150 µm. If defects induce an increase in leakage current under the reverse conditions, the density of the defects can be estimated to be 104–105/cm2. This value is 5–10 times larger than the density of dislocations in single crystal diamond substrate.

Abstract: The packaged microwave 4H SiC pin diode chips (with i-region length of 6 μm, mesa diameter of 80 μm and blocking voltage of 1000 V) were investigated. We studied the parameters of diode I−V curve (in particular, the diode resistance RS at forward current) and the processes of diode switching from forward current of 50 mA to reverse voltage of 15 V, as well as C−V curves, in the 20−700 °C temperature range. At a voltage of 300 V, the diode reverse current was 10 (180) μA when temperature was 600 (700) °C. At a forward current of 40 mA, the diode resistance first decreases smoothly as temperature is increased from 20 up to 300 °C, and then grows up. As temperature is increased from 20 up to 700 °C, the effective lifetime τeff grows from 7 up to 50 ns, while the diode capacitance (in the 0−40 V reverse voltage range) grows smoothly as temperature is increased from 20 up to 400 °C.

Abstract: The switching characteristics of 4Н-SiС p-i-n diodes with 6 µm long i-region were investigated in the 20÷500 °С temperature ranges. It is shown that the diode reverse current increases with temperature and does not exceed 10-7 А at temperature of 500 °С (UR = 100 V). The diode resistance rF at forward current of 40 mA decreases as temperature increases from 20 up to 500 °С. The effective minority charge carrier lifetime in the i-region (τр) was determined from the diode switching (from forward current to reverse voltage) characteristics; it was about 5 ns. As temperature increases from 20 up to 500 °С, τр increases by a factor of 3. We discuss the possibility of application of such diodes (i) in microwave switching facilities and (ii) as temperature sensors. A comparison is made between the parameters of 4Н-SiС p-i-n diodes and those of Si p-i-n diodes with comparable values of calculated blocking voltage.