Papers by Keyword: Capacitance-Voltage Measurements

Abstract: In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (D_it). We show that the extracted D_it strongly depends on the calculation of the surface potential due to variations of the integration constant. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the D_it extraction.

Abstract: p-CdTe film has been deposited on n-Si(111) substrate by thermal evaporation technique. The prepared CdTe/Si heterojunction diodes have been annealed at 573K. The capacitance-voltage measurements have studied for the prepared heterojunctions under 2 KHz frequencies. The capacitance-voltage measurement indicated that these diodes are abrupt. The capacitance at zero bias, the built in voltage and the doping concentration increased after annealing process while the zero bias depletion region width is decreased. The carrier transport mechanism for CdTe/Si diodes in dark is tunneling-recombination. From current-voltage measurement at dark, the values of ideality factor are 2.9 and 3.8. The values of reverse saturation current are 3.77×10^-7 and 9.36×10^-8 Amperes.

Abstract: This paper reports the investigation of a root cause of stain formation on the surfaces of diamond-like carbon (DLC) films. The DLC thin films are prepared using a radio-frequency plasma enhance chemical vapor deposition (RF-PECVD) technique with C₂H₄ as a carbon precursor gas. We have observed water spot-like stains on the DLC surfaces after treating the films with a dilute solution of dipropylene glycol monomethyl ether (DPGME). Low voltage-scanning electron microscopy (SEM) is employed to examine the thin layer of agglomerated stains on the surfaces. The results from capacitance-voltage (C-V) measurements show that as-deposited films inherit some trapped charge accumulations within the structure, thereby resulting in the pronounced shift in the flat-band voltage. These trapped charges make the films prone to surface stain formation. Post-annealing of the DLC films at 200 °C in N₂ for 1 h has proven to reduce the trapped charge density, and therefore prevent stain formation on the DLC films.