Papers by Keyword: Channel Length

Abstract: Shorter channel-length and thinner gate-oxide are required for the scaling of design pitch and improving device performance. We explored variations in the channel length and gate oxide thickness for 1700 V 4H-SiC based VDMOSFETs. A design of experiments was applied to cover multiple designs and process conditions. The final device results show that the shorter channel with thinner gate-oxide leads to better device performance including lower on-resistance, higher current and transconductance. However, an increase in the device leakage starts affecting the breakdown voltage thus limiting the scaling for given process conditions, such as Pwell and JFET implants.

Abstract: In this work, variations in the channel length and gate oxide thickness are studied for the design optimization of 3300 V 4H-SiC based VDMOSFETs. For this, a batch of 3 wafers was processed and tested for key device characteristics. The results indicate shorter channel length of 0.5 μm leads to an increase in the drain leakage current, thus affecting the breakdown voltage as well. The thinner gate oxide at 50 nm demonstrates better control of threshold voltage with no variations in the gate leakage current distribution as compared to 65 nm.

Abstract: Short circuit characteristics of 4H-SiC MOSFETs with different channel lengths are studied in this work. The peak drain-source current during the short-circuit period is measured. These results show that short channel devices has lower capability to sustain short-circuit condition. This work found an evident current tail after the gate turning off. Through the investigation with different device design, circuit condition and numeric simulation. The cause of the current tail is found to be due to the increased ionization of electron-hole pair as the junction temperature is elevated at long short-circuit condition.

Abstract: Production yield is a major factor for semiconductor device manufacturing. To produce high performance devices cost efficiently, it is important to know the process windows of the implemented production technology. This can influence the yield in different ways. One of the critical steps is the photolithography. In this work the impact of misalignment within the technological limits is analyzed and discussed. 4H-SiC VDMOS Transistors were produced and the electrical characteristics were compared with the overlay accuracy of the devices. Small change in channel length can lead to large impact on the electrical characteristic. Especially when the channel length reaches values near to the critical length for short channel effects (SCEs), small overlay inaccuracies influence the electrical characteristic of the devices in an increasing manner. Different cell designs were analyzed regarding their robustness to misalignment.

Abstract: In this paper, we have analyzed the effect of chiral vector, temperature, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage a CNTFET provides over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector pair in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime.