Papers by Keyword: Critical Area

Abstract: In the process of integrated circuit design and manufacturing, dummy metal fill can improve the planarity of layout after Chemical Mechanical Polishing (CMP). However, it will also cause lithography distortion and Critical Area (CA) variation. This paper compares and analyzes the influences of lithography distortion due to metal fill on CA from the perspectives of different defect particles based on 45nm technology node. The results indicate that dummy metal fill can increase open CA after lithography and the defect particle with the diameter of 0.066um leads to the largest increment percentage of open CA, which will take up almost 10%. This paper is instructive in researching dummy metal fill and CA or related fields in the future.

Abstract: As feature dimension of integrated circuits (IC) come into nanometer nodes, yield problems caused by random defects get worse. Even with advanced process techniques, the yield could not achieve 100%. Accurate prediction of yield can point out the direction of process optimization, shorten the production cycle, reduce the production cost, and then increase profits. In this paper, some kinds of random defects which can influence random yield are summarized. Then some widely used yield models are outlined and the drawbacks of these models are analyzed. At last, an improved yield model is proposed with the combination of Poisson model and negative binominal model. This model which takes distributions of random defects into consideration is more flexible and accurate. It can be seen from the simulation results that comparing to those existing models, the improved model indeed has higher fidelity and more flexibility.

Abstract: In the nanometer technology node, the contradiction between high investment and low yield has got more and more prominent, so it plays a very significant role in improving the yield to optimize layout. The COE, Critical area On Edge network, which is a kind of network based on the redundancy material defect with edges expressing critical areas, is constructed in this paper. Vertexes stand for nets of the layout, and edges do short circuit areas existing in nets. By studying the applications of COE in DFM, it is indicated that the COE provides a new way to the research of nanometer node in DFM.