Papers by Keyword: DRAM

Abstract: Carbon-doped Sb-rich Ge-Sb-Te (Sb-CGST) is proved to be a promising candidate for phase change memory because of it high crystallization temperature (higher than 200°C) and 10-year data retention temperature (higher than 120°C). The carbon-doped Sb-rich Ge-Sb-Te (Sb-CGST) films were deposited on SiO₂/Si (100) substrate by RF magnetron co-sputtering using CGST alloy target (a GST target containing 16 at. % C) and Sb targets at room temperature. The content of Sb in the films was controlled by adjusting the sputtering power ratio of CGST and Sb. The results showed that both of these two properties increase firstly and then decreases with increasing the content of Sb, which are superior to that of Ge₂Sb₂Te₅. Furthermore, Sb-CGST based PCM cells were fabricated to investigate the property of material. 6ns pulse could realize SET operation, and 3.2 x 10^-11J energy can realize RESET operation.

Abstract: As semiconductor devices continue to scale down to smaller sizes, high aspect ratio (HAR) structures are required to achieve the desired device performance. As such, wet processing becomes a very challenging process step due to the capillary forces that are generated during drying. The strength of the capillary force is dependent on the surface tension and contact angle of the fluid that is being dried, as well as the feature spacing and AR. If the drying forces are too high (Figure 1), then the features may break or collapse onto each other resulting in poor device yield. Other factors affecting a structure’s susceptibility to collapse include pattern geometry and material composition [1].

Abstract: DRAM industry is not only among the largest manufacturing industries in the world, but also the most competitive. Furthermore, due to DRAM business is characterized by short life cycles, along with highly competition, the manufacturers are forced to migrate to advanced technology quickly. Under this circumstance, the manufacturers have to launch new technology and purchase generational equipment to meet the market demand and reduce manufacturing cost frequently. This paper investigates the technology generational transition of DRAM industry from manufacturing and planning perspectives. The concept of TOC is applied to schedule the production plan of the new/old products. Regarding to shop floor control, three definitions of cycle time are used to diagnose the production status. Finally, the workload ratio of bottleneck is used for the release decision to adjust the rhythm of production.

Abstract: In this paper, we implement and analyze different Network-on-Chip (NoC) designs with Static Random Access Memory (SRAM) Last Level Cache (LLC) and Dynamic Random Access Memory (DRAM) LLC. Different 2D/3D NoCs with SRAM/DRAM are modeled based on state-of-the-art chips. The impact of integrating DRAM cache into a NoC platform is discussed. We explore the advantages and disadvantages of DRAM cache for NoC in terms of access latency, cache size, area and power consumption. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average cache hit latencies in two DRAM based designs are increased by 12.53% (2D) and reduced by 27.97% (3D) respectively compared with the SRAM. It is also shown that the power consumption is a tradeoff consideration in improving the cache hit latency of DRAM LLC. Overall, the power consumption of 3D NoC design with DRAM LLC has reduced 25.78% compared with the SRAM design. Our analysis and experimental results provide a guideline to design efficient 3D NoCs with DRAM LLC.

Abstract: In nano-like or nano-regime trench DRAM products, the product yield usually determines the marketing competition. Due to active area (AA) layer shift in lithography process, the cell leakage and the contact resistance at the source terminal of a cell transistor are increased. These factors will deteriorate the cell integrity in charging and access functions. To monitor this inferiority from lithography deviation, an improved Kelvin measurement and a novel pattern design were recommended. The yield improvement with this technology was really conspicuous.

Abstract: An adequate measurement metrology to nondestructively verify the integrity of dielectric gap-fill in a deep trench (DT) capacitor of deep-submicron DRAM product was proposed. Because of the geometric structure in the DT capacitor, the vertical cylindrical electrode isolator approximately provides a parasitic NMOSFET. Through the electrical measurement, people can analyze these drain-to-source electrical characteristics. Some of most valuable device parameters, threshold voltage (Vt) and mobility (un), correlate to the interface integrity and the surface roughness between silicon substrate and gap-fill oxide (or liner oxide). In other words, as these values are obtained, the degradation level of this interface or gap-fill quality can be clarified. Indirectly, the charge storage quality of this capacitor, avoiding the leakage path, is able to be improved with the process modification.

Abstract: Nanostructures with high aspect ratios, HAR, (ratio of height to lateral feature size) are of interest for many applications. One of the immediate advantages is the large surface area of these structures. In the field of DRAM manufacturing for example, the capacitance of cylindrical DRAM capacitors increases linearly with height. Wet etching and drying of these fragile high aspect ratio structures without lateral collapse (stiction) is a big challenge for the fabrication of DRAM capacitors. The problem with HAR structures is stiction during drying [1]. In order to reduce stiction by improvement of drying techniques, a good metric to quantify the occurrence of stiction is needed. However, currently used methods like SEM or brightfield defect inspection are extremely time-consuming.