Papers by Keyword: Enhancement Mode

Abstract: ZnO NWFETs were fabricated with and without Al₂O₃ passivation. This was done by developing a new recipe for depositing the thin film of ZnO. By using a high donor concentration of 1.7 x 10¹⁸ cm^-3 for the thin film, contact resistance values were lowered (passivated device had R_con = 2.5 x 10⁴ Ω; unpassivated device had R_con = 3.0 x 10⁵ Ω). By depositing Zn first instead of O₂, steep subthreshold slopes were obtained. The passivated device had a subthreshold slope of 225 mV/decade and the unpassivated device had a slope of 125 mV/decade. Well-behaved electrical characteristics have been obtained and the passivated device shows field effect mobility of 10.9 cm²/Vs and the un-passivated device shows a value of 31.4 cm²/Vs. To verify the results, 3D simulation was also carried out which shows that the obtained values of sub-threshold slope translate into interface state number densities of-1.86 x 10¹³ cm^-2 for the unpassivated device and 3.35 x 10¹⁴ cm^-2 for the passivated device. The passivated device is suitable for biosensing applications.

Abstract: In this work, a charge storage based enhancement mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) is proposed and studied. A stacked gate dielectrics, consisting of a tunnel oxide, a charge trap layer and a blocking oxide are applied in the HEMT structure. The E-mode can be realized by negative charge storage within the charge trap layer during the programming process. The impact of the programming condition and the thickness of the dielectrics on the threshold voltage (V_th) are simulated systematically. It is found that the V_th increases with the increasing programming voltage and time due to the increase of the storage charge. Under proper programming condition, the V_th can be increased to more than 2 V. Moreover, It is also found that the V_th increases with the decrease of the thickness of the dielectrics. In addition, it is found that the breakdown voltage of such HEMT can be adjusted by varying the gate dielectric stacks.

Abstract: The static and dynamic characteristics of Complementary JFET (CJFET) logic inverter are studied across a range of temperatures and supply voltages to assess potential improvements in performance of digital logic functions for operation in extreme environments. The logic inverter is truly the core of all digital designs. The design and analysis of inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. At 500 deg C and operating at a supply voltage of 1 V, the CJFET inverter have noise margin comparable to that of room temperature silicon and silicon on insulator CMOS inverters. Furthermore, the static power dissipation by CJFET inverter at 500 deg C is 20.6 nW which is six orders of magnitude lower than that by current SiC technologies, making CJFET technology ideal for achieving complex logic functions, far greater than a few-transistors ICs, in the nearer term.

Abstract: The commercialisation of Silicon Carbide devices and circuits require high performance, miniaturised devices which are energy efficient and can function on the limited power resources available in harsh environments. The high temperature Technology Computer Aided Design (TCAD) simulation model has been used to design and optimise a potential commercial device to meet the current challenges faced by Silicon Carbide technology. In this paper we report a new methodology to optimise the design of high temperature four terminal enhancement mode n-and p-JFETs for Complementary JFET (CJFET) logic.

Abstract: Physics-based analytical models are seen as an efficient way of predicting the characteristics of power devices since they can achieve high computational efficiency and may be easily calibrated using parameters obtained from experimental data. This paper presents an analytical model for a 4H-SiC Enhancement Mode Vertical JFET (VJFET), based on the physics of this device. The on-state and blocking behaviour of VJFETs with finger widths ranging from 1.6+m to 2.2+m are studied and compared with the results of finite element simulations. It is shown that the analytical model is capable of accurately predicting both the on-state and blocking characteristics from a single set of parameters, underlining its utility as a device design and circuit analysis tool.