Papers by Keyword: Focal Plane Array

Abstract: In this paper, a low-cost and modularized test bench for microbolometric focal plane array is proposed. Based on the analysis of driving microbolometric focal plane array, we have set up the simple test bench. The test bench consists of four major modules: optical part, driving sequence timer, power supply and signal processing board, and data analyzer. Each module in the test bench is reconfigurable and the driving sequence timer is programmable in system. The proposed test bench is low-cost and has been applied to practical microbolometric focal plane arrays in our laboratory.

Abstract: Based on viscoplastic Anand’s model, the structural stress of 8×8 InSb infrared focal plane array (IRFPA) detector is systemically analyzed by finite element method, and the impacts of design parameters including indium bump diameters, heights and InSb chip thicknesses on both Von Mises stress and its distribution are discussed in this manuscript. Simulation results show that the maximum stress existing in InSb chip reaches minimum with indium bump diameter 32μm. Under this condition, for the fixed indium height, as the InSb chip thickness reduces from 21µm to 9µm in step of 3µm, Von Mises stress maximum values of InSb chip seems increases gradually, and when the indium bump height reduces from 21µm to 9µm in step of 3µm, its maximum Von Mises stress increase at random increment, do not show certain rules, and indium bump height seems to have a comparable effect on stress value with InSb chip thickness. When indium diameter, height and InSb chip thickness are set to 32µm, 15µm, and 12µm, respectively, the maximal Von Mises value existing in InSb chip reaches minimal value 628MPa, simultaneously the stress distribution at the contacts areas is uniform and concentrated, and this structure is promising to avoid device invalidation.

Abstract: Based on viscoplastic Anand’s model, the structural stress of 8×8 InSb array detector with underfill dependent on indium bump sizes is systemically researched by finite element method. Simulation results show that as the diameters of indium bump decrease from 36μm to 20μm in step of 2μm, the maximum stress existing in InSb chip first reduces sharply, then increases flatly, and reaches minimum with indium bump diameter 32μm. The maximum stress in Si readout integrated circuit (ROIC) fluctuates at 320MPa with amplitude less than 50MPa, almost half stress in InSb chip. Yet the maximum stress in the indium bump array is almost unchangeable and keeps at 16.3MPa. When the height of indium bump increases from 9μm to 21μm in step of 6μm, the maximal stress in InSb chip first reduces sharply from 800MPa to 500MPa, then almost retains constant. With indium bump diameter 32μm and height 21μm, the maximum stresses in whole 8×8 InSb array detector reaches minimum 458MPa, besides, the stress distribution at the contacts areas is uniform and concentrated, the stress value is smallest and this structure is promising to avoid device invalidation.

Abstract: Two-step method is used to research stress and its distribution in 64×64 InSb infrared focal plane array (IRFPA) employing finite element method. First, a small 8×8 InSb IRFPA is studied by changing indium bump diameters from 24μm to 36μm, with indium bump thickness 20μm and InSb thickness 10μm, the simulated results show that von Mises stress in InSb chip is dependent on indium bump diameters, the varying tendency is just like the letter V, here when indium bump diameters is set to 30μm, the smallest von Mises stress is achieved and its distribution in InSb chip is uniform at contacting areas. Then, InSb IRFPA array scale is doubled once again from 8×8 to 64×64 to learn the effect from array size, thus, the stress and its distribution of 64×64 InSb IRFPA is obtained in a short time. Simulation results show that von Mises stress maximum in InSb chip and Si readout integrated circuit almost do not increases with array scale, and the largest von Mises stress is located in InSb chips. Besides, stress distribution on the bottom surface of InSb chip is radiating, and decreases from core to four corners, and stress value at contacting area is smaller than those on its surrounding areas, contrary to stress distribution on top surface of InSb chip.

Abstract: Two-step method is used to research stress and its distribution in 64×64 InSb infrared focal plane array (IRFPA) employing finite element method. First, a small 8×8 InSb IRFPA is systemically studied by varying indium bump diameters, standoff heights and InSb chip thicknesses in suitable range, with indium diameter 30μm, thickness 9μm and InSb thickness 12μm, von Mises stress in InSb chip is the smallest and its distribution is uniform at contacting areas. Then, the sizes of InSb IRFPA is doubled once again from 8×8 to 64×64 to learn the effect from chip sizes, thus, the stress and its distribution of 64×64 InSb IRFPA is obtained in a short time. Simulation results show that von Mises stress maximum in InSb chip almost increases linearly with array scale, yet von Mises stress maximum in Si ROIC decreases slightly with increased array sizes, and the largest von Mises stress is located in InSb chips. Besides, stress distribution on the bottom surface of InSb chip is radiating, and decreases from core to four corners, and stress value at contacting area is smaller than those on its surrounding areas, contrary to stress distribution on top surface of InSb chip.

Abstract: Based on viscoplastic Anand’s model, the structural stress of 8×8 InSb infrared focal plane array (IRFPA) detector is systemically analyzed by finite element method, and the impacts of design parameters including indium bump diameters, heights and InSb chip thicknesses on both von Mises stress and its distribution are discussed in this manuscript. Simulation results show that as the diameters of indium bump decreases from 36 μm to 24 μm in step of 2 μm, the maximum stress existing in InSb chip reduces first, increases then linearly with reduced indium bump diameters, and reaches minimum with indium bump diameter 30 μm, the stress distribution at the contacts areas is uniform and concentrated. Furthermore, the varied tendency has nothing to do with indium bump standoff height. With indium bump diameter 30 μm, as the thickness of InSb chip reduces from 21 μm to 9 μm in step of 3 μm, the varying tendency of the maximum stress value in InSb chip is just like the letter U, as the indium bump thickness decreases also from 21 μm to 6 μm in step of 3 μm, the maximum stress in 8×8 InSb IRPFA decreases from 260 MPa to 102 MPa, which is the smallest von Mises stress value obtained with the indium diameter 30 μm, thickness 9 μm and InSb thickness 12 μm.

Abstract: Nanotechnology is occurring simultaneously in almost every field with strong interdisciplinary applications which have unique and important characteristics for potential novel and high performance devices. Quantum dots grown by epitaxial self-assembly via Stranski- Krastanov growth mode have many favorable properties for infrared sensing. Because of their very small size and three-dimensional confinement, the electronic energy levels are quantized and discrete. These quantum effects lead to a unique property, “phonon bottleneck”, which might enable the high operating temperature of infrared sensing which usually requires cryogenic cooling. Here we report a focal plane array (FPA) based on an epitaxial self-assembled quantum dot infrared detector (QDIP). The device structure containing self-assembled In0.68Ga0.32As quantum dots with a density around 3×1010 cm-2 was grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). Using different structures, we successfully developed QDIPs with a peak photoresponse around 5 μm and 9 μm. High peak detectivities were achieved at 77 K from both QDIPs. By stacking both device structures, we demonstrated a two-color QDIP whose peak detection wavelength could be tuned from 5 μm to 9 μm by changing the bias. 256×256 detector arrays based on 5 μm and 9 μm-QDIPs were fabricated with standard photolithography, dry etching and hybridization to a read-out integrated circuit (ROIC). We demonstrated thermal imaging from our FPAs based on QDIPs.