Papers by Keyword: G-V

Abstract: A systematic study on the 3C-SiC/SiO₂ interface has been done. 3C-SiC epilayers have been grown on a Si (001) substrate. Results obtained from room temperature conductance-voltage (G-V) and hi-low capacitance-voltage (C-V) on n-type 3C-SiC/SiO₂ metal-oxide-semiconductor capacitors (MOS-Cs) have been reported using various types of oxides. The oxides used in these studies have been thermally grown at different oxidation temperatures - 1200°C, 1300°C and 1400°C. Also, the interface trap density (D_it) of as-grown MOS-C is compared with nitrided (thermally grown oxide + N₂O post-oxidation annealing) oxides. Oxide grown at 1300°C followed by N₂O-passivation at the same temperature gives the lowest D_it of 6x10¹¹ cm^-2eV^-1 at 0.2eV from the conduction band (CB) edge.

Abstract: The effect of annealing temperature on the properties of c-Si wafer/SiO_x interface (x = 1.15 and 1.3) is studied by Transmission Electron Microscopy and Capacitance/Conductance-Voltage measurements. Furnace annealing for 60 min at 700 and 1000 °C is used to grow amorphous or crystalline Si nanoparticles. The high temperature process leads to an epitaxial overgrowth of the Si wafer and an increase of the interface roughness, 3-4 monolayers at 700 °C and 4-5 monolayers at 1000 °C. The increased surface roughness is in correlation with the higher density of electrically active interface states.