Papers by Keyword: Interpolator

Abstract: This paper describes an interpolation algorithm in the multi-axis motion control system, which can achieve six-axis interpolation operations, greatly improving the processing efficiency. Using modular design idea on the Quartus II platform, by DDA interpolation theory, interpolation modules are built through VHDL. And these interpolator modules are connected into schematic diagrams. By those schematic diagrams a linear interpolator, a circular interpolator and a composite interpolator are formed. The corresponding functions of those interpolators have been simulated on the Quartus II platform. The simulation shows that this interpolation algorithm is effective to complex multi-axis motion control system.

Abstract: In this paper, a novel architecture of Pythagorean Hodograph (PH) curve interpolator based on Nios Ⅱ embedded processor and FPGA is proposed. The whole interpolator including NiosⅡ processor is built in a single FPGA chip. The interpolator uses a two-stage interpolation scheme to reduce the computational burden of PH curve interpolator. The Nios Ⅱ embedded processor implements 1st-stage interpolation, the FPGA receives the command from the Nios Ⅱ processor and implements 2nd-stage interpolation simultaneously. Therefore, the interpolator can implement the real-time PH curve interpolation algorithm steadily to meet the needs of high-speed and high-precision machining.

Abstract: The architectural scheme of the designed Sigma-Delta DAC on the FPGA is considered. The place of the interpolator in Sigma-Delta DACs is briefly discussed. The summarized structure of the most common interpolators is presented. More applicable structures of interpolators were suggested and analyzed, providing the comparison with [1]. Having changed the structure of the incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude frequency response with a smaller number of non-zero coefficients and much lower FPGA resources. The paper provides simulated results of the interpolator filter transmission characteristics as well as Sigma-Delta modulator quantization noise parameters. It is demonstrated that simulation of the complete converter system (interpolator + modulator + output filter) allows to identify places of the interpolator, where hardware resources could be saved, thereby reducing the chip area occupied by the converter, which is not always obvious when analyzing nodes separately. Therefore another version of the interpolator was proposed for the system ensuring larger suppression of the additional frequency band in the whole system compared with the previous interpolator. Simulated results related to occupied chip resources are also confirmed by the experiment, which was implemented in Xilinx Spartan FPGA.

Abstract: In this paper, the shortcomings of the NURBS interpolator based on Taylor expansion were analyzed and shown clearly based on studying the definition and characteristic of the NURBS curve. The length function and inverse length function were employed in the length calculation of the singularity NURBS curve. The inverse length function was used to validate the length calculating of the NURBS curve. At last, a robust NURBS interpolator algorithm with singular knots was proposed.