Papers by Keyword: Monolithic Integration

Abstract: Several 1.2kV 4H-SiC Bi-Directional MOSFETs (BiD-MOS) design approaches were successfully fabricated and evaluated based on their electrical characteristics. Both monolithic integration design approaches exhibited negligible differences in conduction, blocking, and switching characteristics when compared to their 2-Chip counterpart. However, during the short-circuit withstand time testing, severe gate oscillations were observed in the 2-Chip design, which was not an issue present in either monolithic configuration. As a result of its robust electrical behavior, monolithic integration emerges as a promising design approach for developing efficient and reliable Bi-Directional Switches.

Abstract: In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and 1700-V VDMOSFET devices on a single 4H-SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reach-through in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV, was then conducted to verify the breakdown voltage (V_BD) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (V_BD) exceeding 2000 V.

Abstract: New and original medium power multi-terminal SiC monolithic converter architectures are investigated with vertical switching cells based on SiC JBS diodes and VDMOS transistors. 2D TCAD and mixed-mode Sentaurus™ simulations are performed to optimize switching structures as Buck, Boost, H-bridge high-side row chip common drain-type and low-side row chip common source-type. The proper operation in the turn-on and turn-off of each cell is also studied and validated. To fabricate these new monolithic integrated architectures, two main technological bricks have been developed, for vertical insulation and the integration of a top Ni metal via. To achieve the vertical insulation deep trenches are necessary combining dry plasma and wet KOH electrochemical etching through the thick N⁺ substrate.

Abstract: We report on a new fabrication process of integrated PIN photodetectors with very high quantum efficiencies into a 0.35μm CMOS process, including improved processing for bottom antireflective coating (BARC). The integration process is such that complete modularity of the CMOS process remains untouched by the implementation of the highly efficient photodetectors. Due to the fact that only two additional masks and one ion implantation step are necessary for the implementation of PIN photodetectors including BARC, this integration process also proves to be very cost effective. In-house processed p-doped intrinsic layers with EPI doping levels as low as 1∙10¹²/cm3 serve as CMOS base material. This is a doping level that major semiconductor vendors could not provide. With just one additional mask and ion implantation we provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photodetectors highly benefit from the low doping concentrations of the intrinsic EPI. Special surface protection techniques are performed to maintain the low doping concentrations of the substrate during the complete CMOS processing. To further enhance the photosensor’s quantum efficiency especially of photodetector arrays we present a new BARC process. With this new BARC process we can lower the dark current in photodiode arrays by at least one order of magnitude compared to currently established plasma-etch methods. The following photodiode parameters could be accomplished for 100x100μm2 single photodiodes with BARC: quantum efficiencies of 76%, 99.8% and 74% at wavelengths of 500nm, 675nm and 850nm, respectively, capacitances of 0.13pF and dark currents of 1.18pA for unbiased photodiodes.

Abstract: In this paper, a novel monolithically integrated flexible thermal flow sensor combining four resistors in a Wheatstone bridge including hot-film resistor, temperature-compensating resistor and two other balancing resistors on one chip is proposed in order to improve the system integration level and sensor performances, such as signal to noise ratio (SNR), power consumption and temperature compensation. Fabricating the sensor directly on a flexible polyimide printed circuit board (PCB) by incorporating printed circuit technique with micromachining sputter technique is adopted. A complete performance test on the flow sensor demonstrates its superiorities on power consumption, SNR and temperature drift, the error of which is eliminated from 43% to 8% over a range of ambient temperature (35–75°C).

Abstract: For the first time, a 1200 V 4H-SiC power MOSFET with a monolithically integrated gate buffer circuit has been demonstrated successfully. The device used a 6x10¹⁵ cm^-3 doped, 10 μm thick n-type drift layer to support 1200 V. The gate buffer circuit was built in a p-well, formed by boron ion implantation. The integrated device provided sufficient voltage isolation for the control circuit from the drain of the power MOSFET, and supported internal supply voltages up to 20 V. The operation of the integrated devices was demonstrated. A specific on-resistance (R_on,sp) of 20 mΩ-cm² was observed. The high R_on,sp was due to the limitations in NMOS pull-up circuit topology and the body effect in the 4H-SiC NMOSFET. Development of PMOS pull-up devices is recommended for future integration efforts.

Abstract: The monolithic integrated technology of MEMS was discussed. First discussed the advantages and difficulties faced by the MEMS monolithic integration technology. Second the features and the process of the mainstream MEMS monolithic integration technology was introduced. And finally put forward a SOI MEMS monolithic integration technology, the technology with no high-temperature process, Post-CMOS integrated solution, compatible with the CMOS process. This technology can achieve high aspect ratio, high-performance micro-inertial devices..

Abstract: In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

Abstract: Dense photonic integration requires miniaturization of materials, devices and subsystems, including passive components (e.g., engineered composite metamaterials, filters, etc.) and active components (e.g., lasers, modulators, detectors). This paper discusses passive and active devices that recently have been demonstrated in our laboratory, including monolithically integrated short pulse compressor utilized with silicon on insulator material platform and design, fabrication and testing of nanolasers constructed using metal-dielectric-semiconductor resonators confined in all three dimensions.

Abstract: We designed the monolithic opto-electronic integrated circuit composed by Resonant Tunnelling Diodes (RTD) and Heterojunction Phototransistor (HPT). Circuit simulation of RTD and HPT integration is firstly processed. The material structure and technological process of the device is introduced in detail. A good characteristic is obtained with high Peak-to-valley current ratio.