Papers by Keyword: Post Oxidation Annealing

Abstract: In this work, we report on the engineering of the SiC/SiO₂ MOS interface using H₂ treatments along with NO POA to improve the interface characteristics and device reliability. Significantly low D_it of 3×10¹¹ eV^-1cm^-2, stable threshold voltage, and long gate oxide lifetime > 10⁵ s have been achieved by H₂ annealing before NO POA of thermal SiO₂. Through device electrical characterization and material analysis, we show that the performance enhancement is due to the reduction of interface defects and trapped charges in the SiO₂ surface layer after the POA treatment, which in turn, significantly suppresses the threshold voltage instability.

Abstract: In this work, we demonstrate SiC/high-κ MOS capacitors with low leakage density of 10^-8 Acm^-2, good device uniformity, good thermal stability (> 800 °C), and longer oxide lifetime > 10⁴ s simultaneously. This is enabled by using atomic layer deposition (ALD) processed- HfAlO as the gate dielectric with a thickness of 35 nm, smooth surface (RMS roughness =0.70 nm), and high-quality SiC/ HfAlO interface with interface density (D_it) of 8×10¹⁰ eV^-1cm^-2.

Abstract: In this work, we report an innovative approach to improve the interface properties of SiC/SiO₂ metal oxide semiconductor (MOS) capacitors. High temperature (1350°C) oxidation under different ambient is followed by a combination of post-oxidation annealing (POA) treatments using N₂, N₂O and NO gases. TOF-SIMS analysis shows silicon and nitrogen peaks near the SiC/SiO₂ interface. The silicon peak is attributed to the emission of silicon and carbon atoms during high temperature oxidation. The accumulation of nitrogen is caused by the presence of nitrogen during oxidation or POA. One of the lowest interface-trap densities along with good dielectric strength has been demonstrated with the N₂ and NO gas POA treatment.

Abstract: In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

Abstract: We study the impact of different nitric oxide (NO) post oxidation annealing (POA) procedures on the on resistance R_on of n-channel MOSFETs and on the threshold voltage shift ∆V_th following positive bias temperature stress (PBTS). All samples were annealed in an NO containing atmosphere at various temperatures and times. A positive stress voltage of 30 V was chosen which corresponds to an electric field of about 4.3 MV/cm. The NO POA causes a decrease in overall ∆V_th for longer NO POA times and higher NO POA temperatures. As opposed to the change in ∆V_th, the device R_on increases with NO POA temperature and time.

Abstract: MOS capacitors have been fabricated on (0001), (11-20) and (000-1) oriented 4H-SiC under different post-oxidation anneal (POA) conditions. 100 MHz conductance measurement shows the generation of very fast donor-type interface traps after NO anneal for both Si-face (0001) and a-face (11-20), but not on C-face (000-1). Fast traps were not observed in POCl₃ annealed samples for any orientation. Smallest D_it (at 0.2 eV below conduction band edge) was obtained on Si-face using POCl₃ anneal (1.4x10¹¹ cm^-2 eV^-1), on a-face using NO anneal (2.5x10¹¹ cm^-2 eV^-1) and on C-face using POCl₃ anneal (4.5x10¹² cm^-2 eV^-1).

Abstract: A high-temperature process is used to enhance the CO_x desorption rate to reduce trap density in SiC/SiO₂ interface for SiC MOSFETs. Interface state density as measured by Terman method and C-ψs method for the oxidation processes at a high temperature of 1350°C show significant improvement compared to traditional Si thermal oxidation temperature of 1200°C. The higher oxidation temperature led to a much faster growth rate and some observable hysteresis in the CV curves, which could be due to electron trap and can be resolved by NO_x post oxidation anneal (POA).

Abstract: 3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.

Abstract: Post-oxidation anneals that introduce nitrogen at the SiO2/4H-SiC interface have been most effective in reducing the large interface trap density near the 4H-SiC conduction band-edge for (0001) Si face 4H-SiC. Herein, we report the effect of nitridation on interfaces created on the (11 20) a-face and the (0001) C-face of 4H-SiC. Significant reductions in trap density (from >1013 cm-2 eV-1 to ~ 1012 cm-2 eV-1 at EC-E ~0.1 eV) were observed for these different interfaces, indicating the presence of substantial nitrogen susceptible defects for all crystal faces. Annealing nitridated interfaces in hydrogen results in a further reduction of trap density (from ~1012 cm-2 eV-1 to ~5 x 1011 cm-2 eV-1 at EC-E ~0.1 eV). Using sequential anneals in NO and H2, maximum field effect mobilities of ~55 cm-2 V-1s-1 and ~100 cm-2 V-1s-1 have been obtained for lateral MOSFETs fabricated on the (0001) and (11 20) faces, respectively. These electronic measurements have been correlated to the interface chemical composition.