Papers by Keyword: SOI

Abstract: This paper presents how to improve specific o n-state resistance (Ron) induced by the HCI of a SOI LDMOS device. In manufacturing of UHV device, trade-off between on state resistance and breakdown voltage is always present. But with our process design we are able to improve Ron degradation without compromising the-breakdown voltage. In our design the peak electric field is under gate near source side, due to low electric field near drain helps to increase the current flow much better hence it helps to improve Ron and Vth. If the peak field is located near drain side, the hot holes is easy to penetrate to field oxide and avoid current flow then it causes increase in the Ron.Our simulation results shows 0.27% and 0.95% Ron and Vth increases respectively even at 1e5 second stress time .The Ron degradation phenomenon was analyzed with the 2-D simulation of electric field and impact ionization generation.

Abstract: This paper presents the fabricationof SOI micro-accelerometer by using the sacrificial process. The structure ofthe SOI micro-accelerometer is designed and analyzed by the finite element modeling.As for the fabrication issue, the problem of electrode metal layer to standagainst HF etching is first studied. Second, to prevent the over-etching of theBOX layer during structure releasing process, the etching rate of the BOX layeris carefully investigated and an optimal etching duration is obtained. Third,the adhesion phenomenon between comb fingers during releasing process isstudied and optimized finger geometry is proposed to solve such problem.Devices based on the sacrificial process is carried out successfully, themeasurement results show that the sensitivity of the accelerometer is about 35mV/g, with a maximal measurement error of 12mg, and a maximal nonlinear error of0.41% within 50g.

Abstract: A new kind of SOI LAPS sensor array with trench and heavy doping structure was proposed. Photo current response, noise isolation and device performance were simulated with ISE-TCAD tools. The new structure LAPS sensor array effectively improves noise separation characteristics of adjacent array units. The SNR (signal-to-noise ratio) of LAPS array with trench-isolated structure is superior to that with only heavy doping regions. Trench isolation structure also improves the integration scales of LAPS array.

Abstract: The two different fabrications of the Micro-Electro-Mechanical Systems (MEMS) mirrors were compared: a single-crystal-silicon (SCS)-based micromachining and a silicon-on-insulator (SOI)- based micromachining. While the SOI parts had significantly smaller curved device appearance, they were outperformed in most areas by the SCS parts. This was due primarily to the smaller stress factor in the device layer in the SOI parts compared to the polysilicon layer used in the SCS parts.

Abstract: A high performance lateral silicon photodiode was designed on a Silicon–on-insulator (SOI)-based substrate with SiGe/Si quantum dot technology. The device has the potential of being a serious candidate for applications in sensing applications as well as in optical fiber communications. Five device process parameters and two device noise factors were identified to make the virtual device design insensitive to variation in the selected fabrication parameters. An L9 array from Taguchi method was used to optimize the device design. The simulator of ATHENA and ATLAS were used for photodiode fabrication process and electrical characterization, respectively. The results obtained for responsivity and frequency response after the optimization approach were 0.36 A/W and 21.2 GHz respectively which correspond to the optimization value for the intrinsic region length of 6 μm, photo-absorption layer thickness of 0.505 μm, incident optical power of 0.5 mW/cm² and bias voltage of 3.5 V. As a conclusion, the optimum solution in achieving the desired high speed photodiode was successfully predicted using Taguchi optimization method.

Abstract: The mean projected ranges and range straggling for energetic 200 500 keV Yb ions implanted in silicon-on-insulator (SOI) were measured by means of Rutherford backscattering followed by spectrum analysis. The measured values are compared with Monte Carlo code (SRIM2012) calculations. It has been found that the measured values of the mean projected range are good agreement with the SRIM calculated values; for the range straggling , the difference between the experiment data and the calculated results is much higher than that of .

Abstract: The influence of GBs contained in the channel of MOS-FETs - fabricated in thin SOI layers - is demonstrated. The drain current measured at room temperature increases about 50 times for nFETs and about 10 times for pFETs, respectively, as compared to reference devices. The observations might be interpreted as a strong increase of the mobility of charge carriers. Moreover, the observed stepwise changes of the drain current at 5 K may point to Coulomb blockades.

Abstract: One way to further increase performance and/or functionality of Si micro-and nanoelectronics is the integration of alternative semiconductors on silicon (Si). We studied the Ge/Si heterosystem with the aim to realize a Ge deposition free of misfit dislocations and with low content of other structural defects. Ge nanostructures were selectively grown by chemical vapor deposition on periodic Si nanoislands (dots and lines) on SOI substrate either directly or with a thin (about 10 nm) SiGe buffer layer. The strain state of the structures was measured by different laboratory-based x-ray diffraction techniques. It was found that a suited SiGe buffer improves the compliance of the Si compared to direct Ge deposition; plastic relaxation during growth can be prevented, and fully elastic relaxation of the structure can be achieved. Transmission electron microscopy confirms that the epitaxial growth of Ge on nanostructured Si is free of misfit dislocations.

Abstract: Conventional super-junction lateral double diffused MOSFET (SJ-LDMOS) fabricated on Silicon on Insulator (SOI) substrate suffers from low breakdown voltage under the same on-resistance due to substrate-assisted depletion effect. To suppress this effect, it is important to find the charge density in the inversion layer under buried oxide. In this paper, we propose a charge density equation and its formulation. The results were used in a 3D device simulator to optimize the device structure. The experimental results confirm that the equation is useful to optimize device performance. The breakdown voltage of structure increased 54% and on-state-resistance decreased 58% compared to conventional SJ device. The device fabrication procedure is fully compatible with mainstream SOI CMOS process.

Abstract: In order to develop the SOI micro-accelerometer front release process, this paper discusses in details the key technologies of the process. There are three problems need to be resolved: the corrosion of the electrode, the corrosion rate of the buried silicon dioxide layer as well as the anti-adhesion of the micro-structure. The corrosion characteristic of the electrode is studied, and a metal electrode of high ability of anti-HF acid corrosion is designed, after release of the micro-structure, the electrode does not fall off. The corrosion property of the buried silicon dioxide is studied, and the corrosion rate is exactly known for 2um and 5um thick buried silicon dioxide layer. Based on this, the buried silicon dioxide layer etching time can be controlled, preventing over-etching of the oxide layer. The adhesion of comb fingers and the mass with the substrate is settled at last. By electron microscopy tests, found that the process can get a good micro-structure surface, with smaller footing effects. By test, the sensitivity of the accelerometer is about 144.5mv/g.