Papers by Keyword: Single Wafer Tool

Abstract: For integrated circuit fabrication on 300 mm wafers, copper interconnections cleaning is generally done with single wafer tools. In this study, we focused on the cleaning of aluminum interconnections, on single wafer tool, with a cheap and easy to use chemistry. Aluminum compatibility with diluted HF solutions was first evaluated, then short and efficient cleaning processes were developped for two kind of applications : cleaning after aluminum line etching and cleaning after final dielectric etching over the aluminum pad. It was demonstrated that cleaning efficiency was poor for the shorter process time (20 s), but improved with process time increase, highlighting a lift-off mechanism for polymers removal. Best process was achieved with 40 s of HF 0.2%, that offers a good compromise between polymer removal and lateral recess of the aluminum.

Abstract: Selective nitride etching in semiconductor manufacturing is currently performed in wet benches using hot orthophosphoric acid at 160-180C. This process requires silica seasoning to achieve the desired selectivity to silicon oxide. Silica seasoning in wet benches is achieved by etching blanket silicon nitride wafers prior to running productions runs. While, this method of selective silicon nitride etching has been successful in the past, particle requirements at advanced nodes [1] are driving the need for a new solution. Single wafer wet processing is proposed as a way to meet these challenging new particle specifications.

Abstract: As the DRAM design rule has been smaller, the leaning normally occurred in storage pattern with high aspect ratio also appears in STI (shallow trench isolation) pattern of sub 4Xnm device. IPA (isopropyl alcohol) showing the excellent ability to replace DIW (de-ionized water) is necessary in order to meet the leaning free condition, because the spin drying method cannot satisfy with leaning free condition.

Abstract: Integrating multiple gate oxides on a same die requires a proper definition of their respective active area (fig. 1). First the thick gate oxide is grown, and covered by some photoresist. Then a wet etch removes this oxide on the die areas where the resist has been developed. Finally, after resist stripping and surface cleaning, the thin gate oxide is grown. The interaction between the thick oxide surface, the resist and the etchant makes the wet etch challenging. This paper deals with some characterizations and solutions to improve this process.

Abstract: In the conventional wet cleaning process of contact holes landing on the Si substrate and WSi metal gate, the ILD BPTEOS bowing and CD enlargement were often found by using dilute HF solution. With the device design rule decreasing, the CD size control and cleaning efficiency enhancement are highly demanded. In this work, the high aspect-ratio contact (AR~10) cleaning in single wafer (SW) tool was demonstrated in 58nm flash device. With the facilitation of nano-spray function to enhance particle removal efficiency (PRE), AM1 cleaning in SW tool can achieve the low contact resistance and tighten Rc distribution with less ILD film damage and lower CD enlargement. The parameter dependency of SW tool, including chemical injection method, nozzle swinging effect and nano-spray function, on contact resistance was also investigated. Compared to AM1 cleaning in bench tool, AM1 process in SW tool performs the larger process window for less ILD film damage at higher temperature and concentration.

Abstract: In this study, we used an SEZ single-wafer spin-processor to develop a single backside cleaning solution able to remove any metallic or exotic contaminants by etching a few angstroms of the wafer backside, whatever its coating (no coating, Si3N4 or SiO2). An H2O:H2O2:H2SO4:HF mixture was selected because it allowed independent control of the etch rate on the 3 materials of interest, without roughening to much the silicon surface. Chemistry efficiency was then checked on wafers intentionally contaminated with various metals, and on “production wafers” contaminated during exotic materials deposition or classical copper processes.