Papers by Keyword: Step Bunching

Abstract: We perform the first-principles calculations on the 4H-SiC(0001) surface and clarify the mechanism of the facet formation. We first identify atomic structures of single-, double- and quadribilayer steps and find that the single-bilayer (SB) step has the lowest total energy among these three step structures. Then, we reveal that the nanofacet consisting of SB steps is more energetically stable than the equally spaced SB step and the surface-energy variation caused by the difference of stacking sequences of the bi-atomic layer near the surface is an important factor of the facet formation.

Abstract: We have grown epitaxial layers on 2° off-cut 4H-SiC(0001) Si-face substrates. The epitaxial layer surfaces on 2° off-cut substrates are more prone to generate step-bunching than on 4° off-cut substrates, which are observed by confocal microscopy with differential interference contrast. We have speculated that the step-bunching is generated at the beginning of an epitaxial growth. Triangular defect density of epitaxial layers on 2° off-cut substrates is as low as 0.7 cm^–2 for the size corresponding to 150 mm. We have firstly reported distribution of 2° off-cut epitaxial layers for the 150-mm size using two 76.2-mm wafers: σ/mean = 3.3% for thickness, σ/mean = 7.3% for carrier concentration.

Abstract: Under specific and reproducible conditions we observed that the top bilayer of a spiral step can detach from the remaining bunched step. This dissociated bilayer is located in the middle of a terrace. In this work we detail the parameters for which the spiral step dissociation appears. Furthermore the possible origins of this effect and the reasons why the dissociated step is located in the center of a terrace are discussed.

Abstract: The growth of homoepitaxial layers on off-oriented 6H-SiC substrates proceeds via step flow growth. Such epilayers can exhibit irregularities like step bunching, splicing or crossover of steps. The effects of the substrate off-orientation and growth temperature show an influence on formation of surface irregularities. The mean features seem to be given by the growth mode competition of two-dimensional growth to the step-flow growth.

Abstract: The production of 150 mm-diameter SiC epi-wafers is the key to the spread of SiC power devices. Besides, step-bunching free surface leads to high-performance devices. We have developed the production technology of the epitaxial growth with smooth surface morphology for 4º off Si-face 4H-SiC epitaxial layers on 150 mm diameter substrates. The various area observations of the surface by optical surface analyzer, confocal microscope and atomic force microscope revealed that there was no conventional step-bunching in whole wafer surface. While creating step-bunching free surface is more difficult for thicker epilayer growth, we have achieved step-bunching free surface for 30-μm thick epilayer on a 150 mm diameter substrate. The typical values of thickness uniformity of the 30μm-thick epilayer are 0.5% (σ/mean) and 1.7% (range/mean). A few interfacial dislocations (IDs) were detected for the 150 mm-diameter epi-wafer by reflection X-ray topography. We have succeeded in removal of IDs by the optimized growth condition.

Abstract: It has been widely accepted that wide-band-gap semiconductor SiC can provide low-loss semiconductor switches and diodes for the power electronics applications. The SiC devices enable the low-loss and compact converters and inverters.

Abstract: In this paper we study the surface morphology of <11-20> 4° degree off, silicon terminated, 4H Silicon Carbide (4H-SiC) in terms of growth parameters and post growth argon thermal annealing. We find that out-of-equilibrium conditions favor the reduction of the surface roughness. Furthermore, we find preliminary indications that the same growth parameters that lead to the reduction of the surface roughness promote also a reduction of (1,3) and (4,4) stacking faults density.

Abstract: Chemical vapour deposition in a cold wall reactor working at atmospheric pressure was used to study the homoeptaxial growth of 4H-SiC on 4°ff misoriented substrates from silane and propane precursors. The effect of various growth parameters (temperature 1450-1650°C, C/Si ratio 1-7, thickness 2.5-10 µm) were studied in order to determine the best conditions for obtaining smooth surfaces after epitaxy. It is shown that the main source of roughness is surface undulation which easily appears during growth, especially at low C/Si ratios and high temperature (up to 1600°C). Temperatures above 1600°C and C/Si ratio of 1 give the best results. When reducing temperature, a trade-off has to be found between defects formation and surface undulation.

Abstract: Surface and interface morphology of thermal oxides grown on 4-off (0001) oriented 4H-SiC substrates by dry O2 oxidation was investigated using atomic force microscopy (AFM) and transmission electron microscopy (TEM). When step bunching was present on a starting wafer, oxide surface roughness was much larger than that of the starting 4H-SiC surface. This is attributed to the difference in oxidation rate between the terrace and the step face. A step-terrace structure on 4H-SiC(0001) was mostly preserved on the oxide surface, but pronounced oxidation occurred around the step bunching. Cross-sectional TEM observation showed that the SiO2/4H-SiC interface became smoother than the initial surface and the thickness of the SiO2 layer fluctuated. Such SiO2 thickness fluctuation may cause a local electric field concentration when a voltage was applied to the oxide, thus degrading the dielectric breakdown characteristics of 4H-SiC metal-oxide-semiconductor (MOS) devices.

Abstract: Flat and well-ordered surfaces of silicon carbide (SiC) substrates are important for electronic devices. Furthermore, researchers have reported that 4H-SiC surface roughness increases by step-bunching during epitaxial growth and annealing. Degradation of device properties induced by surface roughening is of great concern. Therefore, a method to reduce this surface roughening is requested. We have developed a damage-free planarization method called catalyst-referred etching (CARE). In this paper, we planarized 4H-SiC substrates and evaluated the processed surface before and after the epitaxial growth. Then, we reduced the step-bunching on the epi-wafer surface and determined the electrical properties of the Schottky barrier diodes (SBD) on the processed surface.