Papers by Keyword: Wafer Thinning

Abstract: This study aims to develop an electrochemical assisted fixed-abrasive lapping (ECAL) process for thinning 4H-SiC wafers (C-face). Process with 20 wt% NaNO₃ electrolyte to generate a softened passivation layer has been formed and simultaneously removed by a fixed diamond lap wheel. Electrochemical tests using a potentiostat have verified 20 V as the selected experimental potential, and a significant reduction in hardness has been confirmed by nanoindentation. Under these conditions, the 4-inch wafer has achieved a material removal rate (MRR) of 3.181 μm/h with wafer quality (Bow –7.80 μm, Warp 48.50 μm, TTV 7.70 μm). When the same conditions have been applied to 6-inch wafers, an MRR of 2.457 μm/h and wafer quality (Bow –5.00 μm, Warp 36.70 μm, TTV 6.60 μm) have been obtained. These results have demonstrated the scalability of ECAL for larger SiC substrates, offering potential for next-generation device manufacturing.

Abstract: This paper shows results of SiC Schottky diodes fabricated without ion-implanted P-type regions. Diodes with blocking voltages up to 4,500 V are demonstrated utilizing an epitaxial P-type ring with sloped edges for the edge termination. Reverse-bias currents at temperatures higher than 60°C, and at nominal blocking voltages of 650 V, 1200 V, and 1700 V, are shown to match the theoretical values based on the two fundamental current mechanisms: tunneling and thermionic emission. In comparison to JBS and MPS diodes, the whole anode area is active, which enables homogeneous current flow and comparable isothermal characteristics without the usual wafer thinning. In addition, the non-thinned wafer results in larger thermal capacitance, allowing for higher repetitive peak surge currents for the same junction temperature within the maximum operating temperature of 175°C.

Abstract: This work presents the influence of Thin Wafer und Laser Anneal Technology on the electrical performance of 4HSiC devices. Substrate thinning and backside ohmic contact formation via laser annealing were successfully applied to in-house designed and manufactured 6 A 650 V SiC diodes at IISB, improving its forward characteristics. The given devices exhibit an on-state voltage drop (V_F) reduction from 1.78 V to 1.62 V at 6 A rated current while maintaining blocking capabilities of more than 1.1 kV with leakage currents less than 1 μA at 650 V nominal voltage. On-resistance (R_ON) was lowered by approx. 30 % to 90 mΩ and 60 % to 12 mΩ in Schottky and conductivity modulation state, respectively. Wafer thinning also allows reducing the influence of non-homogeneous distributed substrate doping concentrations, leading to a more narrow distribution of the forward characteristics of the devices across the wafer.

Abstract: Silicon wafer is machined by diamond cutting tools to certain extent, the cutting tool currently used is polycrystalline diamond (PCD). However, as its cutting edges are not leveled to the same height, it will produce different depth of cut and the stress distribution is uneven on wafer surfaces, in the process of wafer thinning, both the workpiece and the cutting tool are probably damaged, this will increase the production cost accordingly. In this paper, a strategy is described to improve the ability of cutting tool for wafer thinning, a cutting tool named Ultimate Diamond Disk (UDD) designed by Taiwan Wheel Company is recommended, which can reduce both the crack of workpiece and the wear speed of cutting tool. Moreover, an experiment on base of different machining parameters including rotation speed of spindle, feed rate and depth of cut was tested and discussed. As a result, the removal mode of workpiece material and the wafer thinning characteristics of UDD are obtained.

Abstract: We investigated the influence of various backside thinning techniques on the fracture strength of thinned single crystalline silicon wafers by means of ring-ball breaking tests and atomic force microscopy (AFM). In the case of wafer grinding the mean breaking force of samples depends on the surface roughness after fine grinding. Subsequently applied stress-relief processes spin-etching, CMP polishing and plasma dry etching lead to a strong increase of breaking force by a factor of 6 to 15. The three different stress-relief techniques resulted in the same maximum values of breaking force. However, the required amount of material removal is specifically different and also depends on the conditions of initial grinding step. The results will help to identify optimum wafer thinning sequences in the field of MEMS devices and future applications of ultra-thin and flexible integrated circuits.

Abstract: Warpage on the backside of silicon wafer after thinning process is examined. The thinning process includes back-grinding (BG) and wet chemical etching (WCE). Results of wafer warpage were compared to sub-surface damage from Transmission Electron Microscopy (TEM) analysis and showed that sub-surface damage on the backside of the silicon 100 would induce high wafer warpage, and reduced wafer strength. Further studies from surface roughness and topography of each surface finish is obtained by Atomic Force Microscopy (AFM) and SEM show that low surface roughness is in accordance with smooth surface condition, which comes after the wet etching process.

Abstract: Sintered polycrystalline diamond (PCD) compacts are normally used for cutting tools, drill bits and wire dies. A novel application of PCD has been developed to use its entire surface carved to create different patterns which are triangle or square shape loaded with leveled millers that can shave brittle materials in ductile mode. Due to numerous cutting edges formed on the same level of PCD tools, which can be used to thin the wafer surface to achieve both flatness and smoothness of the industrial requirements. SEM has been used to observe the surface and subsurface of the thinned wafer surface. The critical depth of cut between ductile and brittle cutting mode is close to 2 µm in this thinning operation. The damaged layers of machined surface have been observed and studied in this paper.

Abstract: In this initial phase of work, two methods of backside wafer thinning using ICP plasma etching of two-inch SiC substrates have been considered. Plasma processes were optimized for nonbonded and bonded wafers. The non-bonded process was used to etch 250μm thick substrates to a final thickness of 100μm. The bonded process was used to etch glass bonded SiC substrates mechanically ground to 130μm thick and plasma etched to a final thickness of 100μm. Etch rate measurements and surface analysis were performed using a profilometer and white light interferometry. Etch rates of 3.4μm/min were achieved for the bonded process and 2.0μm/min for the non-bonded process. The surface morphology for the non-bonded process was three to four times lower than the bonded process. The part mechanically ground samples showed evidence of surface damage from the grinding process after plasma etching.