Papers by Author: Andriy Hikavyy

Abstract: Epitaxial growth requires a clean starting surface for the growth of a high-quality crystalline layer. For epitaxy on Si, an HF-last wet clean followed by an in-situ high-temperature hydrogen bake is the reference pre-epi clean sequence to obtain an oxygen-free surface [1, 2]. The temperature required to remove all residual oxygen also makes the surface atoms mobile, resulting in reflow. The high temperatures used during the H₂-bake can also result in intolerable doping profile changes. A lower temperature pre-epi clean sequence is required to avoid this reflow, especially when moving away from Si. In addition the high temperatures needed during a H₂-bake would result in the relaxation of high mobility channels, e.g. strained Si_1-xGe_x or III-V materials [3]. Several low temperatures pre-epi cleaning solutions have been proposed in the past, e.g. GeH₄-assisted H₂-bake [4] or more recently, a GeH₄-assisted HCl clean [5]. In this study we looked at the interaction between HF-last wet clean and the in-situ GeH₄-assisted HCl clean prior to Si_0.8Ge_0.2-on-Si epitaxy.

Abstract: Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

Abstract: Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].