Papers by Author: Fabrizio Tamarri

Abstract: The electrical characteristics of MOSFETs fabricated on 4H-SiC with a process based on N implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface up to 6  1019 cm-3. The field effect mobility improves with increasing N concentration. At room temperature values change from 4 cm2/Vs for the not implanted sample up to 42 cm2/Vs for the sample with the highest N concentration. Furthermore, the field effect mobility increases with temperature and presents values above 60 cm2/Vs at 200 °C. The MOSFETs with the better electrical characteristics (higher mobility, lower threshold voltage, lower subthreshold swing) were fabricated by a low thermal budget oxidation process, thank to the use of a high N implantation dose able to produce an amorphous SiC surface layer. A strong correlation among the increasing of the N concentration at the SiO2/SiC interface, the reduction of the interface state density located near the conduction band and the improvement of the MOSFETs performance was obtained.

Abstract: The current-voltage characteristics of Al+ implanted 4H-SiC p+n junctions show an important reduction of leakage currents with diode aging at room temperature. The case of a family of diodes that immediately after manufacture had forward current density increasing from 10-9 to 10-6 A/cm2 when biased from 0 and 2 V, and had a reverse leakage current density of @ 5×10-7 A/cm2 when biased at 100 V, is here presented and discussed. During diode manufacturing a post implantation annealing at 1600 °C for 30 min was followed by a 1000 °C 1 min treatment for metal contacts alloying. After 700 days of storage at room temperature, the diode reverse current density reached an asymptotical value of @ 4×10-11 A/cm2 that is four order of magnitude lower than the initial one. A 430 °C annealing that was made after 366 days is responsible of a decrease of one of these four orders of magnitude, but it does not interrupt the decreasing trend versus increasing time. This same annealing has been effective also for minimizing forward current for bias < 2 V, and sticking the diode turn-on voltage on 1.4 V and the current trend on an ideality factor of 2. These results show that in Al+ implanted 4H-SiC p+n junction there are defects that have an annihilation dynamic at very low temperatures, i.e. room temperature and 430 °C.

Abstract: Aiming to minimize the interface state density, we fabricated MOS capacitors on n-type 4H-SiC by using wet oxidation of nitrogen implanted layers. We investigated a wide range of implantation dose, including a high dose able to amorphise a surface SiC layer with the intent to reduce the oxidation time. The oxide quality and the SiO2-SiC interface properties were characterized by capacitance-voltage measurements of the MOS capacitors. The proposed process, in which nitrogen is ion-implanted on SiC layer before a wet oxidation, is effective to reduce the density of interface states near the conduction band edge if a high concentration of nitrogen is introduced at the SiO2-SiC interface. We found that only the nitrogen implanted at the oxide-SiC interface reduces the interface states and we did not observe the generation of fixed positive charges in the oxide as a consequence of nitrogen implantation. Furthermore, the concentration of the slow traps evaluated from the Slow Trap Profiling technique was low and did not depend on the nitrogen implantation fluence.

Abstract: This work reports the realization and characterization of 4H-SiC p+/n diodes with the p+ anodes made by Al+ ion implantation at 400°C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6×1019 cm-3 and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600°C to 1700°C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 0-cm measured for the sample annealed at 1700°C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased, respectively, from 93% to 47% and from 2×10-7 Acm-2 to 1×10-8 Acm-2 at 100 V reverse bias, for increasing post implantation annealing temperature.