Papers by Author: H.L. Fiedler

Abstract: Based on silicon on insulator (SOI) technology [, a monocrystalline membrane is fabricated, in which a buried silicon dioxide layer in the silicon material is the sacrifice layer for the cavity. The membrane is a monocrystalline silicon top layer which contains nanoholes for creating the cavity in the buried oxide (BOX). To encapsulate the cavity the holes are sealed by using different techniques like non-stressed plasma-enhanced chemical vapour deposited (PECVD)-nitride and-oxide, thermal oxidation and evaporation of aluminum. To determine the sticking behavior of the membrane different sizes of membranes are fabricated and compared due to their sticking behavior. The experimental result shows that a membrane, having the size of 25 μm × 25 μm or below, has a perfect non-sticking behavior and can be used for further fabrication (cf. Fig. 8). For comparison, Figure 9 shows a membrane which delivers sticking behavior. The knowledge of this work can be widely used for several applications that need a cavity with a monocrystalline membrane like an absolute pressure sensor with a fully integrated CMOS-circuit on top of it [. This delivers a large variety of possibilities for novelty MEMS devices in different fields of research.

Abstract: Multiple Patterning Seems to Be One of the Most Promising Solutions for the Gap between the 193 Nm Immersion Lithography and the 13.5 Nm EUV Lithography for Industrial Manufacturing of Ultra Large Scaled Integrated CMOS Circuits [1]. the Used Techniques in this Paper Lead to an Excellent Homogeneity and Uniformity of the Channel Length and Width which Enables a Fundamental Statistical Analysis of the Electrical Transistor Parameters. the Process Flow Has Been Optimized to Minimize the Active Channel Area and to Achieve a Sufficient Yield for a Trustworthy Statistical Analysis. while the Channel Length Is Defined by a Single Deposition- and Etchback Technique the Active Area Is Defined by a Composition of Multiple Spacers that Lead to a Diffusion Stop Barrier. the Statistical Analysis of these Devices Shows Dramatically Increasing Fluctuations of the Threshold Voltage if the Device Dimensions Are Decreased.

Abstract: The standard Local Oxidation of Silicon (LOCOS) technique uses different oxidation rates of silicon and Low Pressure Chemical Vapour Deposited (LPCVD) silicon nitride in steam ambient to structure the field oxide. Due to different coefficients of thermal expansion a pad oxide is needed at the boundary layer to prevent stress from the substrate. This leads to a lateral diffusion of oxygen, also known as “birds beak”, which limits the minimum structure size to a few 100 nm [1]. When scaling down to this dimension, the Shallow Trench Isolation (STI) has become the standard isolation technique for fabrication of high-performance semiconductors to allow a high package density. Unfortunately the STI-process uses Chemical Mechanical Polishing (CMP) which increases the process complexity and leads to high costs. Therefore a new method which uses a low stress Plasma Enhanced Chemical Vapour Deposited (PECVD) silicon nitride without a pad oxide at the boundary layer will be presented in this paper.