Papers by Author: H. Takahashi

Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.

Abstract: In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.