Papers by Author: Heu Vang

Abstract: A polyimide (PI) has been used for the passivation of maximum 7.8 kV 4H-SiC P+N–N+ (PiN) diodes with a 60 µm-thick base epilayer and a junction termination extension (JTE) periphery protection. The dielectric strength of PI films is studied versus area and temperature. The reverse electrical characterization of the PI–passivated PiN diodes is presented for different natures of the environmental atmosphere. The results are compared to those obtained from same devices passivated with a deposited SiO2 thick film. The highest experimental breakdown voltages are obtained for PI–passivated PiN diodes immersed in PFPE oil, with a 5-6 kV typical value, and a 7.3 kV maximum value. Experimental observations are discussed in correlation with the insulating film properties.

Abstract: N+ 4H-SiC commercial substrates with n-type epilayers have been used to realize bipolar diodes and TLM structures. The p-type emitter of diodes was realized by Al implantations followed by a post-implantation annealing with or without a graphite capping layer. Ohmic contacts were formed by depositing Ti/Ni on the backside and Ni/Al on the topside of the wafer. It appears that capping the sample during the annealing reduces considerably the surface roughness and the specific contact resistance. Sheet resistance and specific contact resistance as low as 2kΩ/□ and respectively 1.75×10-4 Ωcm² at 300 K have been obtained. I-V measurements as a function of temperature have been performed from ~100 to ~500 K. The variations of the series resistance vs. temperature can be explained by the freeze-out of carriers and by the variation of carrier mobility.

Abstract: Silicon carbide devices limitations often originate from the quality of the substrate material. Therefore it is interesting to investigate devices fabricated on alternative source materials. Currently, CREE is the world market leader of SiC wafers. Nowadays, some new companies begin to propose alternative material. The European manufacturer SiCrystal furnishes now some epiwafers for the fabrication of 1,2kV devices. In this paper we present 4H-SiC 1.2 kV pin diodes with a JTE termination realized on a SiCrystal epiwafer. The devices exhibit a blocking voltage of 1.2 kV, a current density of 420 A.cm-2 and a specific differential series resistance of 4.4 m-⋅cm2. The yield of fabricated diodes with a breakdown voltage greater 600 V is superior to 75%.

Abstract: 6H and 4H–SiC epilayers were Al-implanted at room temperature with multiple energies (ranging from 25 to 300 keV) in order to form p-type layers with an Al plateau concentration of 4.5×1019 cm-3 and 9×1019 cm-3. Post-implantation annealing were performed at 1700 or 1800 °C up to 30 min in Ar ambient. During this process, some samples were encapsulated with a graphite (C) cap obtained by thermal conversion of a spin-coated AZ5214E photoresist. From Atomic Force Microscope measurements, the roughness is found to increase drastically with annealing temperature for unprotected samples while the C capped samples show a preservation of their surface states even for the highest annealing temperature. After 1800°C/30 min annealing, the RMS roughness is 0.46 nm for the lower fluence implanted samples, slightly higher than for unimplanted samples (0.31 nm). Secondary Ion Mass Spectroscopy measurements confirm that the C cap was totally removed from the SiC surface. The total Al-implanted fluence is preserved during postimplantation annealing. A redistribution of the Al dopants is observed at the surface which might be attributed to Si vacancy-enhanced diffusion. An accumulation peak is also observed after annealing at 0.29 9m, depth corresponding to the amorphous/crystalline interface that was determined on the as-implanted samples by Rutherford Backscattering Spectroscopy in channeling mode. The redistribution of the dopants has an impact on their electrical activation. A lower sheet resistance (Rsh= 8 k
) is obtained for samples annealed without capping than for samples annealed with C capping (Rsh= 15 k
).