Papers by Author: James A. Cooper

Abstract: In this work, we demonstrate a novel oxidation-free gate oxide process consisting of a two-step surface preparation treatment, followed by atomic layer deposition of SiO₂ and a post-deposition anneal in nitrogen. The surface treatment includes a 1300°C anneal in hydrogen and dilute silane, followed by decoupled plasma nitridation (DPN). Long channel MOSFETs fabricated with this process show a 1.5X improvement in peak field effect mobility compared with devices utilizing a standard thermal oxide and NO anneal. The MOSFETs had a positive threshold voltage, low gate leakage, and a breakdown field of nearly 10 MV/cm.

Abstract: SiC power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from their theoretical limits of performance. At blocking voltages above 1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and JFET regions. Trench MOSFETs have smaller cell area than planar DMOSFETs, and are inherently more scalable. Both Rohm and Infineon devices have cell pitches of about 3 μm per active channel. In this paper we demonstrate a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs”.

Abstract: Silicon Carbide (SiC) power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from theoretical limits of performance. Above ~1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and the JFET regions. Trench MOSFETs generally have smaller cell area than planar DMOSFETs and are inherently more scalable. In this paper, we describe a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs.”

Abstract: Silicon carbide (SiC) is enabling the next generation of semiconductor power devices, with performance orders-of-magnitude beyond silicon. The most important power switching device is the SiC power MOSFET, whose performance is limited by three main resistance elements: the channel, drift layer, and substrate. For blocking voltages in the range of 400-900V, substrate resistance is a major limitation. Wafer thinning is currently used to reduce the substrate resistance, but this also reduces the strength of the wafers. We report on a waffle substrate technique that relies on wafer thinning and inductively coupled plasma (ICP) etching to reduce the substrate resistance below levels achievable by thinning alone, while retaining the mechanical stability of a moderately-thinned substrate. This technique can be applied to any SiC device for which substrate resistance is a limitation.

Abstract: A new class of power MOSFET, the vertical tri-gate MOSFET, is described and analyzed. The structure can reduce the 4H-SiC MOS channel resistance by up to an order-of-magnitude, producing the same benefit as if the mobility were increased by the same factor. In this paper we outline the fabrication procedure and describe the unit processes unique to this structure.

Abstract: Silicon carbide (SiC) trench MOSFETs, or UMOSFETs, generally exhibit lower specific on-resistance than planar DMOSFETs due to a more compact unit cell, higher electron mobility on the a-face surface, and the absence of a JFET region. In this paper we compare the performance of two types of trench UMOSFETs based on 2-D Sentaurus^TM Device simulations, and show that the single-trench oxide-protected structure exhibits ~40% lower specific on-resistance and half the peak oxide field of the double-trench design when both are optimized for maximum figure of merit.

Abstract: In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance R_on,sp and blocking voltage V_BR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

Abstract: We have designed, simulated, fabricated, and characterized high-voltage 4H-SiC p-channel DMOS-IGBTs on 20 kV blocking layers for use as the next generation of power switching devices. These p-IGBTs exhibit significant conductivity modulation in the drift layer. The maximum currents of the experimental p-channel IGBTs are 1.2x and 2.1x higher than the ideal 20 kV n-channel DMOSFETs at room temperature and 175°C, respectively.

Abstract: We compare the on-state and switching performance of high-voltage 4H-SiC n-channel DMOSFETs and p-channel IGBTs within a three-dimensional parameter space defined by blocking voltage, switching frequency, and current density. We determine the maximum current density each device can carry at a given switching frequency, such that the total power dissipation is 300 W/cm2. The IGBT current depends strongly on lifetime in the NPT buffer layer, and only weakly on lifetime in the drift layer. The MOSFET current is essentially independent of frequency.

Abstract: We describe an optimized design for the 1 kV short-channel 4H-SiC power DMOSFET, obtained from numerical simulations using the Taguchi method. Three new structural features are employed: (1) a current spreading layer (CSL) below the p-well, (2) a heavily-doped, narrow JFET region, and (3) a segmented p-well contact.