Papers by Author: Kazuto Takao

Abstract: A simple and practical method of characterizing traps at SiC/SiO₂ interfaces close to the bottom of the conduction band by using the split C−V and Hall measurements is proposed. This technique was applied to the characterization of traps at a wet-oxidized SiC/SiO₂ interface on C-face and those at an oxynitrided SiC/SiO₂ interface on Si-face. It was shown that the density of traps near the conduction band of the oxynitrided SiC/SiO₂ interface was more than 10 times larger than that of the wet-oxidized SiC/SiO₂ interface.

Abstract: We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (R_onA_active) of 12 mW·cm². The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.

Abstract: In this paper, we found origin of V_F degradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A V_F degradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered V_F degradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.

Abstract: 13-kV 4H-SiC PiN diodes were fabricated on 4° and 8° off-axis substrates and their electrical properties were examined. Small test PiN diodes with various JTE concentrations were fabricated and the dependence of JTE concentration was examined. The highest breakdown voltages were 14.6 and 14.1 kV at a JTE1 concentration of 1.9 × 10¹⁷ cm⁻³ for both the 4° and 8° off-axis substrates. Based on the results, 4 mm × 4 mm SiC PiN diodes were successfully fabricated and exhibited avalanche breakdown voltages of 14.0 and 13.5 kV for the 4° and 8° off-axis substrates, respectively. Forward voltage degradation was larger for the 8° off-axis substrates.

Abstract: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

Abstract: Previous simulation works and experiments on the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (Vbd) and the on-state resistances (RonS) of the Super-SBDs based on Baliga’s figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: Vbd and RonS. The Vbd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the Vbd by the doping concentration is not similar to the simulation result. And the RonS are about 3.22 mcm2 which is higher than that of simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.01016 cm-3 and mesa-shaped termination structure, have excellent Vbd of 2990 V which is almost same as that of simulation result and RonS of 3.22 mcm2.

Abstract: The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm2 and excellent dynamic characteristics.

Abstract: A passivation annealing in nitric oxide (NO) ambient significantly reduces the interfacial defects of the SiO2/4H-SiC interface and improves the inversion MOS channel mobility. Effects of the nitridation in NO ambient become more pronounced at high temperatures in general. However, the maximum process temperature in a standard hot-wall oxidation furnace is restricted around 1200oC due to the softening point of quartz. Meanwhile, by use of a cold-wall oxidation furnace, high temperature and short time thermal processes become possible. In this study, we have developed an extremely high temperature (>1400oC) rapid thermal processing for the gate oxidation in the 4H-SiC DIMOSFET fabrication process. The peak MOS channel mobility of lateral MOSFETs on the DIMOSFET chip shows as high as 19cm2/Vs. The specific on-resistance of the device was 12.5m
cm2 and the blocking voltage was 950V with gate shorted to the source.

Abstract: This paper reports the first demonstration of the lifetime control of the minority carrier in 4H-SiC PiN diodes by He+ ion implantation. In this work, we fabricated 4H-SiC PiN diodes with the epitaxial junction and the blocking voltage of 2.6kV, precisely corresponding to the theoretical blocking voltage calculated from the doping concentration (4.0x1015/cm2) and the thickness of the drift layer (16.5 µm). He+ ion implantation was performed with the energy and the dose of 400kV and 1.0x1013-2.0x1014/cm2, respectively. We observed no different characteristics in the blocking voltage (2.6kV) and leakage current (<10µA@2.5kV) between the PiN diodes with/without He+ ion implantation. However, we confirmed the improvement of the current recovery characteristics in the diodes with He+ ion implantation.