Papers by Author: Konstantinos Rogdakis

Abstract: Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowire (NW) were fabricated. Devices with rectifying Source (S) and Drain (D) contacts have been observed. In contrast with the ohmic-like devices reported in the literature, the Schottky contact barrier (SB) at S/ D regions acts beneficially for the FET performance by suppressing the off-current. At high positive gate voltages (>10 V), the Schottky barriers tend to be more transparent leading to ION/IOFF ratio equal to ~ 103 in contrast to the weak gating effect of the ohmic-contacted 3C-SiC NWFETs.

Abstract: Silicon microwires (MWs) previously synthesized using the VLS method with gold catalyst are being carburized at 1100°C under methane aiming to their conversion to SiC. SEM, TEM as well as XPS and Raman spectroscopy were used for structural and morphological characterization. After carburization achievement, SiC is found to be polycrystalline with a high density of stacking faults associated to an increase of surface roughness. Directions for the carburization process optimization are given.

Abstract: Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowires (NWs) were fabricated and electrical characterization is presented. Silvaco simulation was used to fit the I-V characteristics and to extract information about the carrier (electrons) concentration and the oxide/NW interface quality. The high trap density and fixed charges at the nanowire/oxide interface, Dit~5x1011 cm-2eV-1 and Qf ~3x1013cm-2, and the high electron concentration (~3x1019 cm-3) originating from unintentional doping severely affect the electrical conduction through the nanowires which has as a result low values of mobility and transconductance, 0.11 cm2/Vs and 7x10-10 A/V, respectively.

Abstract: In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate, various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.

Abstract: 3C-SiC is a promising material for high power and high-speed electronic devices as well as in sensors operating at high temperatures or hostile environments. For these reasons, we solved self-consistently the Poisson equation within the quantum Non Equilibrium Green Function Formalism (NEGF) in order to model and compare 3C-SiC and Si nanowire (NW) Field Effect Transistors (FETs) operating in ballistic regime (at room temperature 300 K). As a general conclusion of our calculations, Si and SiC NW FETs have almost the same electrical behavior: they depict the same subthreshold slope and have similar on currents [ION/IOFF (SiC)~81 % ION/IOFF (Si) in case of 4 nm NW cross section side].