Papers by Author: Michele Sanmartin

Abstract: This work takes into account low Al implanted concentrations of 3 x 10¹⁸ cm^-3 and 1 x 10¹⁹ cm^-3 to compare the results of 1600°C and 1950°C post-implantation annealing treatments, done with two different annealing times per given implanted Al concentration and post implantation annealing temperature. Current-voltage and Hall effect measurements were performed to have the drift hole density and the drift hole mobility curves in the temperature range 100 - 650 K. The fitting of these curves in the frame of a carrier transport into the extended states of the valence band were performed to estimate the Al acceptor density, the donor compensator density, and the Al acceptor ionization energy. Peculiar feature of hole density and hole mobility curves is a contemporaneous increase of both carrier density and mobility values with increasing annealing time, which is congruent with the output parameters of the fitting procedure. The latter shows an almost stable Al electrical activation and a decrease of compensation with increasing annealing time for constant annealing temperature and given implanted Al concentration.

Abstract: An inductively heated furnace and an ultra-fast microwave heating system have been used for performing post implantation annealing processes of P+ implanted semi-insulating <0001> 4H SiC at 1800-1950°C for 5 min and 2000-2050°C for 30 s, respectively. Very high P+ implantation fluences in the range 71019 81020 cm-3 have been studied. The annealing processes in the inductive furnace and the one at the lower temperature in the microwave furnace show a saturation in the efficiency of the electrical activation of the implanted P+ that is bypassed by the microwave annealing process at the higher temperature. The measured electron mobility values versus electron density are elevated in all the studied samples and for every post implantation annealing process. This has been ascribed to an elevated implanted crystal recovery due to the very high annealing temperatures > 1800°C.

Abstract: Phosphorous implanted n+/p diodes have been included in the masks for manufacturing n-MOSFET devices and processed in the same way of source/drain regions. The diode junctions were made by a P+ implantation at 300°C and a post implantation annealing at 1300°C. The diode emitter area was protected by 0.6 m thick CVD oxide during the processing of the MOSFET gate oxide. Three gate oxide processes were taken into account: two of them include a N implantation before a wet oxidation, while the third one was a standard oxidation. Considering the effect on the n+/p diodes, the main difference among the processes were the wet thermal oxidation time that ranged between 180 and 480 min at a temperature of 1100°C. The diode current-voltage characteristics show similar forward but different reverse curves in the temperature range of 25-290°C. Differences in reverse bias voltage as a function of the measurement temperature have been analyzed and are related to the different gate oxidation time. A correlation between the shortest oxidation time and the lower leakage current is presented.

Abstract: We report investigations on the fabrication and electrical characterization in the range 27°C -290 °C of normally off 4H-SiC circular MOSFET devices manufactured on p-type semiconductor. An high quality SiO2/SiC interface is obtained by nitrogen ion implantation conducted before the thermal oxidation of SiC. Two samples with different nitrogen concentration at the SiO2/SiC interface and one un-implanted have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. With increasing temperature, in all the samples the threshold voltage decreases and the electron channel mobility increases, reaching the maximum value of about 40 cm2/Vs at 290 °C for the sample with the highest N concentration. The observed improvement of the mobility is related to the beneficial effect of the N presence at the SiO2/SiC interface, which leads to the reduction of the interface trap density with energy close to the conduction band. Our results demonstrate that N implantation can effectively be used to improve the electrical performance of surface n-channel 4H-SiC MOSFETs.

Abstract: Aiming to minimize the interface state density, we fabricated MOS capacitors on n-type 4H-SiC by using wet oxidation of nitrogen implanted layers. We investigated a wide range of implantation dose, including a high dose able to amorphise a surface SiC layer with the intent to reduce the oxidation time. The oxide quality and the SiO2-SiC interface properties were characterized by capacitance-voltage measurements of the MOS capacitors. The proposed process, in which nitrogen is ion-implanted on SiC layer before a wet oxidation, is effective to reduce the density of interface states near the conduction band edge if a high concentration of nitrogen is introduced at the SiO2-SiC interface. We found that only the nitrogen implanted at the oxide-SiC interface reduces the interface states and we did not observe the generation of fixed positive charges in the oxide as a consequence of nitrogen implantation. Furthermore, the concentration of the slow traps evaluated from the Slow Trap Profiling technique was low and did not depend on the nitrogen implantation fluence.

Abstract: Many investigations have been conducted on the growth conditions of SiO2 on SiC to improve the oxide quality and the properties of the silicon carbide-silicon dioxide interface. In this work a comparison between a wet oxidation and an oxidation in N2O ambient diluted in N2 is proposed. The interface state density Dit near the conduction-band edge of SiC has been evaluated by conventional C-V measurements obtaining results similar or better than the literature data. Furthermore, the slow trapping phenomena have been studied and preliminary results are reported.