Papers by Author: Mrinal K. Das

Abstract: The development of 4H-SiC PiN diodes capable of blocking to greater than 10 kV while having current ratings of 20 A at 100 A/cm2 is continuing in earnest. VF instability of these diodes continues to be a roadblock, but progress is being made, and a 20 A/10 kV 4H-SiC PiN diode wafer with an overall device yield of 40% has been fabricated. The latest device characteristics are discussed, along with details of approaches in improving the reverse recovery characteristics of these diodes to satisfy the requirements needed for implementation into high voltage inverter modules capable of switching at up to 20 kHz.

Abstract: SiC IGBTs are suitable for high power, high temperature applications. For the first time, the design and fabrication of 9 kV planar p-IGBTs on 4H-SiC are reported in this paper. A differential on-resistance of ~ 88 m(cm2 at a gate bias of –20 V is achieved at 25°C, and decreases to ~24.8 m(cm2 at 200°C. The device exhibits a blocking voltage of 9 kV with a leakage current density of 0.1 mA/cm2. The hole channel mobility is 6.5 cm2/V-s at room temperature with a threshold voltage of –6.5 V resulting in enhanced conduction capability. Inductive switching tests have shown that IGBTs feature fast switching capability at both room and elevated temperatures.

Abstract: Optimization of the thermally oxidized 4H-SiC MOS interface has produced p-channel lateral MOSFETs with hole inversion layer mobility as high as 10 cm2/Vs. This has been accomplished by identifying the 1200oC Dry, 950oC Wet (un-nitrided) oxidation as ideal for hole conduction across the MOS inversion layer and by implant activation annealing at 1800oC of the heavily implanted n-type well. High temperature measurements show that the high mobility and normally-off operation is maintained throughout the operating temperature range. Oxide leakage measurements yield a dielectric strength of 8.5 MV/cm with 90% yield, thereby enabling the manufacture of high performance p-channel devices like the IGBT.

Abstract: Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

Abstract: Forward voltage (VF) drift, in which a 4H-SiC PiN diode suffers from an irreversible increase in VF under forward current flow, continues to inhibit commercialization of 4H-SiC PiN diodes. We present our latest efforts at fabricating high blocking voltage (6 kV), high current (up to 50 A) 4H-SiC PiN diodes with the best combination of reverse leakage current (IR), forward voltage at rated current (VF), and VF drift yields. We have achieved greater than 60% total die yield onwafer for 50 A diodes with a chip size greater than 0.7 cm2. A comparison of the temperature dependent conduction and switching characteristics between a 50 A/6 kV 4H-SiC PiN diode and a commercially available 60 A/4.5 kV Si PiN diode is also presented.

Abstract: Steady-state and transient characteristics of packaged 6-kV 4H-SiC junction diodes have been investigated in the temperature range Т = 300 – 773 К. Analysis of the forward current-voltage characteristics and reverse current recovery waveforms shows that the lifetimeτ of non-equilibrium carriers in the base of the diodes steadily increases with temperature across the entire temperature interval. The rise in τ and decrease in carrier mobilities and diffusion coefficients with increasing temperature nearly compensate each other as regards their effect on the differential resistance of the diode, Rd. As a result, Rd is virtually temperature independent. An appreciable modulation of the base resistance takes place at room temperature even at a relatively small current density j of 20 A/cm2. At T = 800 K and j = 20 A/cm2, a very deep level of the base modulation has been observed. The bulk reverse current is governed by carrier generation in the space-charge region via a trap with activation energy of 1.62 eV. The surface leakage current of packaged structures does not exceed 2×10-6 А at T = 773 K and a reverse bias of 300 V.

Abstract: The PiN diode is an attractive device to exploit the high power material advantages of 4H-SiC. The combination of high critical field and adequate minority carrier lifetime has enabled devices that block up to 20 kV and carry 25 A. Furthermore, these devices exhibit fast switching with less reverse recovery charge than commercially available Si PiN diodes. The path to commercialization of the 4H-SiC PiN diode technology, however, has been hampered by a fundamental problem with the forward voltage stability resulting from stacking fault growth emanating from basal plane screw dislocations (BPD). In this contribution, we highlight the progress toward producing stable high power devices with sufficient yield to promote commercial interest. Two independent processes, LBPD1 and LBPD2, have been shown to be effective in reducing the BPD density and enhancing the forward voltage stability while being compatible with conventional power device fabrication. Applying the LBPD1 and LBPD2 processes to 10 kV (20 A and 50 A) 4H-SiC PiN diode technology has resulted in a dramatic improvement in the total device yield (forward, reverse, and forward drift yields) from 0% to >20%. The LBPD1 process appears to be more robust in terms of long term forward voltage stability.

Abstract: 8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.

Abstract: We have tested the radiation detection performance of Silicon Carbide (SiC) PIN diodes originally developed as high power diodes. These devices consist of 100 micron thick SiC grown epitaxially on SiC substrates. The size and thickness of the devices make them appropriate for a number of radiation detection applications. We tested 0.25 cm2 and 0.5 cm2 devices and obtained X-ray spectra under illumination with an Am-241 radioactive source. The spectra showed an energy resolution that was consistent with the resolution expected for the large capacitance of the device. Smaller devices with a diameter of 1 mm were also tested and produced spectra with a room temperature energy resolution of ~550 eV, which is consistent with the electronics limit for the capacitance of the small device. We measured the absolute charge generated by X-rays per KeV in SiC by comparing the charge generation with similar silicon devices and determined the energy required per electron hole pair in SiC to be 8.4 eV. We also performed radiation damage tests on these devices and found no significant loss in charge collection up to a photon dose of 100 MRad. Applications for these devices can be found in the fields of particle physics, nuclear physics, nuclear medicine, X-ray fluorescence, X-ray astronomy and X-ray navigation.

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.