Papers by Author: Peter Verheyen

Abstract: Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

Abstract: This paper presents an investigation of the impact of a Highly Doped Drain (HDD) implantation after epitaxial deposition on Si1-xGex S/D junction characteristics. While the no HDD diodes exhibit the usual scaling of the leakage current density with Perimeter to Area (P/A) ratio, this is not the case for the HDD diodes, showing a smaller perimeter current density JP for smaller window size structures, corresponding with larger P/A. This points to a lower density of surface states at the Shallow Trench Isolation (STI)/silicon interface, which could result from a lower compressive stress. In order to examine the role of the HDD implantation damage, Transmission Electron Microscopy (TEM) inspections have been undertaken, which demonstrate the presence of stacking faults in small active SiGe regions. These defects give rise to local strain relaxation and, therefore, could be at the origin of the lower STI/Si interface state density. The window size effect then comes from the active area dependence of the implantation defect formation.