Papers by Author: Rita Vos

Abstract: The vapor-phase deposition of 11-azidoundecyltrimethoxysilanes at reduced pressure and elevated temperature allows the introduction of azido (N₃) functionalized silicon wafer substrates. This process can be optimized by controlling the amount of surface adsorbed water and results in uniform and reproducible self-assembled monolayers (SAMs). The N₃-SAM density as investigated via TOF-SIMS is comparable on thermal oxide and Si₃N₄ substrates. Furthermore, it is demonstrated that biomolecules can be successfully conjugated on both substrates using azide-alkyne ‘click’ reactions.

Abstract: In semiconductor manufacturing of 3-D nano-structures, modified kinetics have been encountered for the aqueous chemical etching of thin films in nano-confined spaces. A popular explanation relies on changes in reactant concentration from the overlap of electrostatic double layers (EDL) on opposite walls of the nano-structures. In this study, the cycloaddition of dibenzylcyclooctyne-PEG3-alcohol (DBCO) to a linear azide-terminated SAM was performed in nanochannels of width varying from 62 to 32 nm. ATR-FTIR was used to monitor the reaction kinetics, characterize water structuring and determine the pH in nanochannels. Reaction kinetics were slower in nanochannels as compared to a planar surface, while pH shifts were observed in absence of EDL overlap, with a significant influence of channel width. Actually only the overall decrease in reaction rate could be explained by EDL overlap. The discussion shows that the water structuring measured in nanochannels may play a significant role in the observed phenomena.

Abstract: Cleaning photoresist from semiconductor wafers during the transistor formation in the front end of the line (FEOL) becomes more challenging with ever smaller nodes. First of all the resists do become more difficult to clean with decreasing node size, because implantation energy increase and the resist becomes more complex (to comply with the reduced wave length of the laser light for the lithography) at future node sizes. This results in more cross linked / polymerized photoresist, which is harder to (wet) strip. Additionally, the requirements on material compatibility of the cleaning solution increase, as more elements are used to build the transistor less than a monolayer of these materials can be removed during a single cleaning step.

Abstract: Following Moores scaling law, the transistor source and drain area become shallower and higher doped regions. As a consequence the limitations of substrate and dopant loss during cleaning become more stringent. For a better understanding, highly B, As and P doped blanket substrates, either prepared by ion implantation or by EPI growth, are studied. Substrate and dopant loss as a function of time and different HF etching conditions is monitored by Inductively Coupled Plasma Mass Spectrometry (ICP-MS) and additional techniques like Spectroscopic Ellipsometry (SE), .... It is shown that in general, the Si etching is dependent of the position of the Fermi level. More remarkably, the junction (4 nm) of a non-annealed heavily As or P doped substrate is completely removed after less than 20 min of etching in HF. This process is related to enhanced etch rates because of the amorphization of the substrate.

Abstract: In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.

Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.

Abstract: With the continuous decrease of feature size of semiconductor devices new process related challenges must be overcome continuously. One of the key issues for technology development is to have the proper metrology in place to evaluate the myriad process steps fast and accurately. Sometimes the mere existence of a particular metrology is not enough because of cost and throughput issues. The goal of this paper is to show that simply by monitoring the background signal of a light scattering tool, certain process optimizations and monitoring can be done much faster while bringing down the cost significantly. We focus particularly on post I/I strip optimization in this paper.

Abstract: In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.

Abstract: The removal of ion implanted photoresist (II-PR) after implantation of ultra shallow extension and halo regions is considered as one of the most challenging front-end-of-line (FEOL) processing steps for 32nm and beyond CMOS technology nodes. Commonly used resist strip processes such as fluorine-based dry plasma ash and hot sulfuric/peroxide mixtures induce unacceptable levels of oxidation and material loss [1-.

Abstract: In FEOL processing, doping of active areas like source, drain, and extensions (NMOS and PMOS) is done by ion implantation. Un-doped regions are covered with photoresist to protect them from implantation. Ion implantation modifies the surface of the photoresist to generate a dehydrogenated amorphous carbon layer, the crust [1]. When the implant conditions are more aggressive (higher implant energy and implant dose), the hard crust becomes more and more challenging to be removed [2]. Conventionally, a plasma ashing process followed by a wet cleaning, typically SPM (Sulfuric acid/Hydrogen peroxide mixture) chemistry, can remove the implanted photoresist, but usually leads to damage and strong oxidation of the underlying semiconductor material and hence result in material or dopant loss. As the technology node migrates beyond 45nm, the photoresist removal process should also be compatible with novel materials such as high-k dielectric and metal-gate used in advanced gate stack integration. For these reasons, it is desirable to eliminate the plasma ash and SPM clean chemistry. Wet only PR removal process is studied using new chemistries like solvents that are compatible with the other FEOL process steps, however, the photoresist removal using solvents only still showed lower removal efficiency than conventional processes. It has been demonstrated that the CO2 cryogenic pre-treatment can improve the ion implanted photoresist stripping efficiency of the wet cleaning processes [3], and can also enhance the photoresist removal efficiency by the solvents.