Papers by Author: S.F. Tzou

Abstract: Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.

Abstract: NiPt self-aligned silicide (salicide) has become a major candidate for the 45nm node due to its better thermal stability and the surface morphology of NiSi on Si substrate [1,2]. SiGe has been proposed for PMOS strain engineering [3]. The relevant SiGe oxidation behavior [4], reaction with platinum [5] and thermal stress behavior [6] are important factors in developing a process for 45nm NiPt salicide over SiGe stressor. These concerns require the review of the current process for NiPt to verify its compatibility and extendibility.