Papers by Author: Tohru Nakamura

Abstract: This paper demonstrates ion implanted lateral GaN MISFETs using double ion implantation technology, which enables us to form Si ion implanted source/drain regions in Mg ion implanted p-well fabricated on free-standing GaN substrates. Maximum drain current of 39 mA/mm and maximum transconductance of 4.5 mS/mm for GaN MISFET with a gate length of 2 μm at an estimated Mg surface concentration of 2.2 × 10¹⁸ cm^-3 were obtained. A threshold voltage was-0.5 V for the device. These results show that we successfully formed Si ion implanted n-type regions in the Mg ion-implanted layer and achieved innovative performance.

Abstract: An effective acceptor level (E_A^eff) for representing the increased ionization ratio in extrinsically photon-recycled p-type GaN is proposed. E_A^eff at 300 K in the range of 0.1360.145 eV is found to reproduce current/voltage characteristics of transmission-line-model patterns formed with GaN p-n junction epitaxial layers and electrode spacing of 320 μm when the p-n diode current flowing through an 80×100-μm electrode is 90 mA. When E_A^eff is decreased from 0.160 eV to 0.145 eV, the on-resistance of 18×100-μm GaN bipolar transistors is predicted to be reduced by more than 50%.

Abstract: This report describes the first to fabricate GaN p-n junction diodes on free-standing GaN substrates with a 3mm diameter. For the diode of 3 mm in diameter, the specific on-resistance and the breakdown voltage were 124 mΩ•cm2 (at 4.0 V) and -450 V, respectively. Consequently, combination of our material and device processing revealed a record fabricated device size with a high breakdown voltage and low forward leakage current in GaN vertical diodes.

Abstract: In this paper, we demonstrate triple ion implanted 4H-SiC bipolar junction transistor (BJT) with etched extrinsic base regions. At the result of etching extrinsic base regions by mask of contact metals, maximum common emitter current gain was improved from 0.7 to 1.6.

Abstract: The impact of CF4 plasma treatment on the surface roughening of SiC has been investigated for N ion implanted SiC(0001) which is implanted with the energy range from 15 to 120 keV at a dose of 9.2 x 1014/cm2. The N ion implanted sample, which is processed by CF4 plasma, shows small surface roughness of 1.6 nm after annealing at 1700 oC for 10 min, while the sample without CF4 plasma treatment shows the large surface roughness (6.6nm) and micro step structure. XPS measurements reveals that CF4 plasma treatment is effective to dissolved the residual oxide on the surface of SiC which is not removed by BHF acid of SiO2 layer on SiC. It is strongly suggested that the formation of micro step structure with the increase of the surface roughness is promoted by the residual oxide such as SiCOx, on SiC.

Abstract: Electrical properties of p+n 4H-SiC(0001) diode formed by Al ion implantation to n-type epitaxial layer have been investigated as a function of Al doping concentration ranging from 1 x 1020 to 6 x 1020 /cm3 and the operation temperature. The n-type 4H-SiC(0001) epitaxial layer with a net donor concentration of 1 x 1016 /cm3 are multiply implanted by Al ions in the energy range from 30 to 170 keV at elevated temperature of 500 oC with a implantation layer thickness of 350 nm, followed by the annealing at 1900 oC for 1min using EBAS. On-state resistance of diode with Al concentration of 1 x 1020 /cm3 is estimated to be about 4.5 mcm2, while that for diode with Al concentration of 6 x 1020 /cm3 is 1.8 mcm2 at 25 oC. In the sample with Al concentration of 6 x 1020 /cm3 shows the positive temperature coefficient of on-state resistance of diode, while that for sample with Al concentration less than 3 x 1020 /cm3 is negative. The diode formed by Al implantation at the concentration of 6 x 1020 /cm3 is able to operate at the constant current density of 80 A/cm2 at the bias of 2.9 V independent to operation temperature.

Abstract: We investigate the structural and electrical properties of polycrystalline 3C-SiC obtained from P ion implanted 4H-SiC with the box-shaped doping profile (NP: 6 x 1020/cm3, thickness: 400 nm, ion dose: 1.6 x 1016/cm2, room temperature). RBS measurement reveals that the highly defective region is formed by P ion implantation, which remains even after annealing at 1700 oC. X-TEM observation shows the P ion induced amorphous layer is recrystallized to twinned-3C-SiC. After annealing at 1300 oC, a sheet resistance of 950 /sq. and sheet carrier concentration of 1 x 1015/cm2 was obtained. By increasing the annealing temperature from 1500 to 1700 oC, the sheet resistance was drastically decreased to about 200 /sq., while there was a small change in the sheet carrier concentration. For the sample annealed at 1700 oC, the electrical activity of the P impurity was estimated to be about 10 % which is comparable to the case of hot implanted sample.

Abstract: It is demonstrated that Si ion implantation is useful to fabricate GaN/AlGaN/GaN HEMTs with extremely low gate leakage current and low source resistance without any recess etching process. The source/drain regions were formed using Si ion implantation into undoped GaN/AlGaN/GaN on sapphire substrate. Using ion implantation into source/drain regions with energies of 30 and 80 keV, the performances were significantly improved. On-resistance reduced from 9.9 to 3.5 Ω·mm. Saturation drain current and maximum transconductance increased from 300 to 560 mA/mm and from 75 to 160 mS/mm, respectively.