Papers by Keyword: A-Face

Abstract: Channel mobility is one of the most critical parameters in 4H-SiC based Power MOSFETs and contributes a significant fraction of device on-state resistance. Experimentally, it has been shown that the a-face channel mobility is much higher compared to the Si-face, making a-face a very attractive option for a wide range of applications in the power electronics market. However, modelling of the a-face channel mobility using Technology Computer Aided Design tools is not well established due to the complex nature of channel mobility due to a variety of scattering mechanisms involved. In this paper, we present a well calibrated a-face channel mobility model that shows an excellent match with the available experimental data and further provides critical insights into the anisotropic nature of channel mobility in 4H-SiC MOSFET structures.

Abstract: In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO₂/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.

Abstract: We study the interface properties of 4H silicon carbide Si-face 0001 and a-face 11220 power MOSFETs using the charge pumping technique. MOSFETs produced on the a-face show a higher electron mobility than Si-face devices, although their charge pumping signal is 5 times higher, indicating a higher interface/border trap density. We show the main contribution to the interface/border trap density on a-face devices originates from deep states in a wide range around midgap, whereas Si-face devices show a higher and exponentially increasing interface/border state density close to the conduction band edge of 4H silicon carbide, resulting in reduced mobility.

Abstract: We experimentally demonstrate 4H-SiC n-channel, DMOS Insulated Gate Bipolar Transistors (IGBTs) on 180 µm thick lightly doped free-standing n^- substrates with an ion-implanted collector region, and metal-oxide-semiconductor (MOS) gate on (0001) and (000-1) surfaces. The IGBTs show an on-state current of 20A/cm² at a power dissipation of 300W/cm². Threshold voltage of 7.5V and 10.5V was obtained on Si-face and C-face respectively. Both IGBTs show a small positive temperature coefficient of the forward voltage drop, which is useful for easy parallelization of devices.

Abstract: In this paper we have investigated the effect of two key processing steps for the fabrication of 4H-SiC trench gate power MOSFETs, namely activation annealing and reactive ion etching on the MOS interface properties of a-face (11-20) 4H-SiC. By optimizing activation annealing conditions, high channel mobility (µ_fe) of 111 cm²/V.s, threshold voltage (V_T) of 3.5V and subthreshold slope (S) of 194 mV/dec was obtained. However, after reactive ion etching (RIE) of the surface, µ_fe reduced to 81 cm²/V.s with increase in V_T to 5V and S to 331 mV/dec. This is possibly due to increase in interface trap density from 1.8×10¹² cm^-2 to 3.3×10¹² cm^-2 after RIE treatment estimated from by MOS gated diode characteristics. Increased trap density contributes to higher coulombic scattering as indicated by the weaker temperature dependence of high field mobility in RIE etched sample.

Abstract: Threshold voltage (V_TH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on V_TH instability is also discussed. Nitridation treatments such as N₂O and NH₃ post-oxidation annealing (POA) are effective in stabilization of V_TH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious V_TH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H₂ POA.

Abstract: Lateral expansion of small mixed polytype 4H/6H-SiC and 6H-SiC slivers were realized by hot wall chemical vapor deposition (HWCVD). Small slivers cut from m-oriented (11 ̅00) SiC boule slices containing regions of 4H and 6H-SiC or just single polytype 6H-SiC were exposed to HWCVD conditions using standard silane/propane chemistry for a period of up to eight hours. The slivers exhibited approximately 1500 μm (1.5 mm) of total lateral expansion. Initial analysis by synchrotron white beam x-ray topography (SWBXT) confirms, that the lateral growth was homoepitaxial, matching the polytype of the respective underlying region of the seed sliver.

Abstract: In-grown type stacking faults (SFs) like structures were observed in 100mm diameter 4H-SiC crystals by Photoluminescence (PL) mappings, and structural analyses using HRTEM clarified that the SF-like structures were comprised of 6H (3, 3) stacking sequences. The stacking sequences of the SF-like structures observed are different from the SFs formed in the a-face grown crystals, suggesting that it is due to 6H nucleation on {0001} plane terraces.