Papers by Keyword: BOE

Abstract: Still nowadays in integrated circuits manufacturing, few materials patterns are defined by a wet etch on patterned deep UV photoresist. From dies to dies generation, an optical performance improvement is required, hence an evolution with thinner and thinner positive resist. This makes these latter more sensitive to wet chemical etchant through the polymer, reducing their protection of the underneath material. Following characterizations enable a clear understanding of BHF (Buffered HF) benefits versus diluted HF during a gate oxide definition.

Abstract: A simple method for the fabrication of silicon nanowires using Electron Beam Lithography (EBL) combined with thermal oxidation size reduction method is presented. EBL is used to define the initial silicon nanowires of dimensions approximately 100 nm. Size-reduction method is employed for reaching true nanoscale of dimensions approximately 20 nm. Dry oxidation of silicon is well investigated process for self-limited size-reduction of silicon nanowires. In this paper, successful size reduction of silicon nanowires is presented and surface topography characterizations using Atomic Force Microscopy (AFM) are reported.