Papers by Keyword: C-V Characteristics

Abstract: In this paper, the radiation resistance of GaN and SiC is compared. The effect of the irradiation temperature on the carrier removal rate in both semiconductors during proton irradiation is considered. It was found that in GaN, as well as in SiC, the rate of carrier removal decreases with increasing irradiation temperature. The dependence of the GaN sample resistance on the radiation dose was also calculated based on a model previously proposed to describe a similar dependence for SiC. Based on the experimental data obtained, it is concluded that the processes of radiation compensation in GaN and SiC are similar.

Abstract: Schottky barrier diodes (SBD) were fabricated on SiC surfaces that had been treated with different surface passivation techniques, so that metal-semiconductor analysis could be used to evaluate the quality of this surface. In this paper, we discuss the results of this study that used Current-Voltage (I-V), Capacitance-Voltage (C-V) and Current-Voltage-Temperature (I-V-T) analysis to look at the impact of untreated oxidation, Nitrous oxide (N₂O) and Phosphorus Silicate Glass (PSG) treatments prior to oxide removal, and the formation of Mo, Ni and Ti diodes. While the results of this study did not reveal any consistent patterns between the different treatments, a Mo diode formed on a surface after PSG treatment, displays exceptionally low leakage (4.44×10^-5 A/cm² at 19°C; 7.26×10^-4 A/cm² at 300°C) given a low barrier height (1.27 eV). Moreover, the barrier heights extracted from C-V analysis before contact annealing show a variation across all the diodes, suggesting that the interface is greatly suffering from Fermi-Level pinning, the result of significant interface traps.

Abstract: In this paper, p-CuO/n-CdS heterojunction was prepared by thermal evaporating CdS thin films on CuO 1 mm thick ceramic pellet substrate. The electrical properties of p-CuO/n-CdS heterojunction were investigated by forward current–voltage–temperature (I–V–T) characteristics in the temperature range of 100-300 K. The junction barrier height, ideality factor, and the series resistance values of the diode evaluated by using thermionic emission (TE) theory and Cheung’s method are 0.566 eV, 5.535 and 618.24 Ω at 300 K, respectively. The junction barrier height, ideality factor and series resistance were found to be strong temperature dependence. In part of C-V measurements at room temperature, the obtained built-in potential value being 0.538 V is well consistent with the junction barrier height value evaluated from I-V measurements

Abstract: The ferroelectric and electrical properties of potassium nitrate (KNO3): polyvinylidene fluoride (PVDF) composite layers prepared by melt press method have been studied. The stability of ferroelectric phase (phase –III) of potassium nitrate (KNO3) in the composite layers at room temperature have been analyzed. The temperature dependence of ferroelectric hysteresis loop (P-E) characteristics have been investigated in the composite layers. The electrical conductivity (σ) and dielectric behaviour of composite layers have been characterized. The conductivity and dielectric variation with temperature during heating and cooling modes has been found to provide the knowledge of phase transition in the composite. The capacitance –-voltage (C-V) and conductance - voltage (G-V) characteristics clearly show the ferroelectric butterfly loop, which is attributed to the features of ferroelectricity in the composite layers at room temperature. The coexistence of ferroelectric phase (phase III) with paraelectric phase (phase II) has also been observed at room temperature in the composite layers during dielectric and conductivity measurements.

Abstract: SiC MIS structure with ultra-thin Al₂O₃ as gate dielectric deposited by Atomic Layer Deposition(ALD) on epitaxial layer of 4H-SiC(0001)8⁰N-/N+ substrate is fabricated. The experimental results indicate that the prepared ultra Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25MV/cm, excellent interface properties(2×10¹³cm^-2•eV^-1) and low gate-leakage current (I_G=1×10^-3A/㎝-²@EOX=8MV/cm). Analysis of current conduction mechanism in deposited Al₂O₃ gate dielectric has also been systematically performed. The confirmed conduction mechanisms consisted of FP emission, FN tunneling, DT and Schottky emission. And the dominance of these current conduction mechanisms depended on applied electrical field, When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4eV, which can meet the requirement of SiC MISFET devices.

Abstract: The Y0.5Yb0.5MnO3 ferroelectrics/HfO2 stacking layer was constructed on Si(100) substrate through the chemical solution deposition. The HfO2 insulating layer crystallized on Si(100) substrates consisted of uniform grains and had smooth surface. The Y0.5Yb0.5MnO3 film prepared on the HfO2 insulator layer had preferred orientation along c-axis. The Y0.5Yb0.5MnO3 film consisted of uniform grains and had smooth surface. The clockwise C-V hysteresis induced by ferroelectric polarization switching was observed in the MFIS structure. The memory window of the MFIS structure was about 2 V and the retention time was over 105 s.

Abstract: The (Y,Yb)MnO3 films were crystallized on Y2O3 layers using alkoxy-derived precursor solutions. As a result of investigation of the effect of the Y2O3 layer on the dielectric properties of the (Y,Yb)MnO3/Y2O3/Si, the crystallographic properties such as the orientation and surface morphology of the (Y,Yb)MnO3 thin films depended on the crystallographic appearance of the insulator layer. Following that, the dielectric properties of the MFIS structures varied. For the construction of excellent MFIS structure, the improvement of the orientation, crystallinity, and surface smoothness of the (Y,Yb)MnO3 film by the optimization of the microstructure and dielectric property of the insulator is necessary.