Papers by Keyword: C-V Measurement

Abstract: We report on the electrical characterization of the Metal-Oxide-Semiconductor (MOS) interfacerealized on in-situ Ge-doped n-type 4H-SiC epilayers grown by Chemical Vapour Deposition(CVD). In order to study the relevance of this novel material for MOSFET technology, and in particularwhether the Ge presence deteriorates the SiC/SiO2 interface, we investigated the electrical propertiesof MOS capacitors realized on this novel substrate. Capacitance-Voltage measurements, performedto determine the quality of the SiC/SiO2 interface, show that the interface traps concentration is notincreased by the Ge content. The current through the oxide layer, monitored to study the bulk oxidequality and the tunneling mechanisms, indicates that Fowler-Nordheim conduction occurs and that thesubstrate-to-oxide barrier for electrons is comparable to the reported values for the SiC/SiO2 system.

Abstract: Electrical properties of the gate oxides thermally grown in N₂O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

Abstract: The effect of the alternative nitridation process of the 4H-SiC/SiO₂ interface by introduction of a thin silicon nitride layer on the electrical properties of the gate oxide has been investigated. C-V and G-V measurements on inversion-channel MOS devices revealed similar results to the conventional N₂O oxidation. Higher field-effect mobility values are achieved due to lower interface roughness of the alternative nitridation process. However, insignificant degradation of the reliability was observed.

Abstract: A plasma enhanced atomic layer deposition process has been demonstrated for Lanthanum oxide films using La (thd)₃ precursor and oxygen plasma. The chemical and electrical properties of La₂O₃ ultra-thin films on Si (100) substrates before and after post-annealing in N₂ ambient have been investigated. X-ray photoelectron spectroscopic revealed that interface reactions take place after annealing process which lead to oxygen insufficiency, as well as the balance band offset decreases with the increase of annealing temperature. The capacitance-voltage and current-voltage characteristics show La₂O₃ capacitors annealed at 900 °C have negligible hysteresis, smaller interface trap density in comparison with as-deposited samples, but larger flat band voltage and higher gate-leakage current density due to the appearance of oxygen vacancy in the La₂O₃ films.

Abstract: This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.

Abstract: 4H-SiC epitaxial films grown on 4H-SiC in CVD reactor VP508GFR are investigated using FTIR, X-Ray diffraction, C-V measurements, stylus profiler and DIC optical microscopy.

Abstract: We have studied the electrical properties of Si p-n junction diodes by deep level transient spectroscopy (DLTS) measurements. The p-n junctions were developed on a Phosphorus doped Si by depositing Al and annealing at various temperatures. In order to confirm junction formation, current-voltage and capacitance-voltage measurements were made. Two deep levels at Ec-0.17 eV (E1) and Ec-0.44 eV (E2) were observed in the DLTS spectrum. These traps have been characterized by their capture cross-section, activation energy level and trap density. On the basis of these parameters, level E1 can be assigned as V-O complex and E2 as P-V complex. These traps are related to the growth of n-Si wafer and not due to Al diffusion.

Abstract: Dense tin oxide based ceramics are a new type of varistor materials. To further understand the electrical properties of SnO2 varistors doped with CoO, Nb2O5, and Cr2O3, the techniques of capacitancevoltage (C-V) measurement and deep level transient spectroscopy (DLTS) were used to investigate the electron traps in the SCN samples (doped with 1.0 mol% CoO and 0.05mol% Nb2O5) and SCNCr samples (doped with 1.0 mol% CoO, 0.05mol% Nb2O5 and 0.05mol% Cr2O3). Two electron traps were detected: trap T1 is located at Ec - 0.30 ± 0.01eV and trap T2 is located at Ec – 0.69 ± 0.03eV for both SCN and SCNCr samples. The variations in the donor density and trap density could be related to the addition of chromium oxide. The features of these traps are discussed based on the defect theory related to the SnO2 varistors.