Authors: Mitsuhiro Kushibe, Johji Nishio, Ryosuke Iijima, Akira Miyasaka, Hirokuni Asamizu, Hidenori Kitai, Ryoji Kosugi, Shinsuke Harada, Kazutoshi Kojima
Abstract: Carrier lifetime in low carrier concentration 4H-SiC epitaxial layers grown on the C-face was enhanced by using carbon implantation and post annealing. The measured carrier lifetime increased with the thickness of the epitaxial layer and was 11.4 µs for the 150 µm thick epitaxial layer. The internal carrier lifetime was estimated as 21 µs from the dependence of the measured carrier lifetime on the epitaxial layer thickness. This value is almost comparable to the reported values of the internal carrier lifetime for the layers grown on the Si-face.
432
Authors: Koji Nakayama, Atsushi Tanaka, Katsunori Asano, Tetsuya Miyazawa, Hidekazu Tsuchida
Abstract: The electrical characteristics of 4H-SiC pin diodes with 8H-type in-grown stacking faults are investigated. The pin diodes have epilayers with low Z1/2 center concentration formed by using the carbon implantation process. The forward voltage drops of the diode with 8H-type in-grown stacking faults are larger than those of the diode without a 8H-type in-grown stacking fault. At room temperature, the differential on-resistance of the pin diode with 8H-type in-grown stacking faults is larger than the value calculated from donor concentration in the drift layer by using the current transportation model of the unipolar device. Meanwhile, the differential on-resistances of the pin diode with 8H-type in-grown stacking faults decrease with an increase in temperature and become smaller than the calculated value at temperature of more than 200 °C.
903
Authors: Koutarou Kawahara, Jun Suda, Tsunenobu Kimoto
Abstract: It has been clarified that Z1/2 center, a well known deep level as a lifetime killer, can be reduced to the concentration below 1011 cm-3 by thermal oxidation or C+ implantation plus Ar annealing. In this study, the authors investigate the trap-reduction phenomena systematically (experimentally), and propose a model to analyze the phenomena. Furthermore, prediction of the defect distributions is realized by solving a diffusion equation in accordance with the trap reduction model. This analytical model can explain almost all experimental data: oxidation-temperature dependence, oxidation-time dependence, and initial-Z1/2-concentration dependence of the defect reduction. Based on these results, the authors accomplish to eliminate the Z1/2 center to a depth of 100 μm in the sample with a relatively high initial-Z1/2-concentration of 1013 cm-3 by thermal oxidation at 1400°C for 16.5 h.
241
Authors: Koji Nakayama, Atsushi Tanaka, Katsunori Asano, Tetsuya Miyazawa, Masahiko Ito, Hidekazu Tsuchida
Abstract: The forward voltage drops of pin diodes with the carbon implantation process or thermal oxidation process using a drift layer of 120 μm thick are around 4.0 V and are lower than those with the standard process. The reverse recovery characteristics of diodes with the standard process or carbon implantation at room temperature show almost the same tendency. In the reverse recovery characteristics at 250 oC, pin diodes with carbon implantation process, however, have the longer reverse recovery time than those with the standard process. These characteristics indicate that a recombination path other than the bulk carrier lifetime, such as the interfaces or the surface recombination, becomes dominant in the reverse recovery characteristics at room temperature.
989
Authors: Koji Nakayama, Ryosuke Ishii, Katsunori Asano, Tetsuya Miyazawa, Masahiko Ito, Hidekazu Tsuchida
Abstract: Forward voltage drops of carbon implanted and thermal oxidized pin diode with thick drift layer are investigated to evaluate the effect on the lifetime. The forward voltage drops of the carbon implanted and thermal oxidized pin diodes with drift layer of 120 μm thick were around 4.0 V. Furthermore, blocking characteristics of 4H-SiC pin diodes with mesa-JTE, which were fabricated on C-face and Si-face substrates, are also investigated. The breakdown voltages of pin diodes with 250 μm and 100 μm epitaxial layers are 17.1 kV and 10.9 kV, respectively.
535
Authors: M. Voelskow, D. Panknin, Efstathios K. Polychroniadis, Gabriel Ferro, Philippe Godignon, Narcis Mestres, Wolfgang Skorupa, Yves Monteil, J. Stoemenos
Abstract: An approach for the defect density reduction in 3C-SiC epitaxially grown on Si is to
improve the quality of the carbonized layer during the early stage of growth. For this reason the conventional carbonization process was replaced by a slower and nearer equilibrium carbonization method. Carbon is introduced by implantation into oxide of an oxidized Si substrate, near the SiO2/Si interface, and then it is transferred to the Si surface by annealing. Good quality 3C-SiC grains are formed embedded into the Si substrate, which are absolutely flat at the SiO2/Si interface.
Another advantage of the new carbonization process is the elimination of the cavities due to the suppression of Si out-diffusion.
233
Authors: Nikolay Djourelov, Takenori Suzuki, Chun Qing He, Yasuo Ito, Kalina Velitchkova, E. Hamada, Kenjiro Kondo
280