Papers by Keyword: Eutectic Bonding

Abstract: Considering the safety of the charge filled in the chambers and the operational reliability, a low temperature eutectic alloy bonding was preferred for the final assembling process of MEMS-based solid propellant microthrusters (SPM) array with top-side igniters. The optimum conditions of the alloy coating are the pH value of the solution is 0.5, the base metal layer is composed of Ti (60nm)/Cu (500nm) deposited by magnetron sputtering. The bonding process was conducted in an oven with air and the bonding temperature is 70°C. To predict the performance of bonding layer, the temperature distributions of eutectic alloy layer were simulated by ANSYS software when the chamber is full of high temperature reactants. The simulation results demonstrated the bonding strength wouldn’t cut down since the heat transfer induced by the combustion of charge. The assembled MEMS-SPM array was tested under constant voltage, the results indicated that the eutectic solder bonding procedure meet the requirements of the MEMS-SPM assembling.

Abstract: In this paper, temperature characteristic of a previous developed nickel-chromium (Ni-Cr) thin film atmosphere pressure sensor is analyzed caused by residual gas. As expected, the output signal of the previous fabricated sensor increases with atmosphere pressures. But when pressure load is fixed, the voltage-temperature characteristic is nonlinear. One factor of this effect is residual gas. Based on the pressure-displacement equation of membrane, the gas balance equation and Provided that the deformation of membrane is spherical crown, the relationship equation of relative change of piezoresistor is defined. Studying the First order derivative and second order derivative of relationship equation of relative change of piezoresistor, it is proved that the residual gas will affect the temperature characteristic of previous designed sensor.

Abstract: Piezoelectric sensor can produce voltage when deflected (function as an energy harvester) while piezoelectric actuator can deflect when a voltage is applied. Different device applications have different requirements on the thickness and in-plane geometry of the Lead Zirconate Titanate(PZT) piezoelectric layers and thus have their own processing difficulties. In this paper, PZT-Au-Si cantilever is fabricated by eutectic bonding and dicing process.The properties of lapped PZT ceramics and silicon cantilever is also evaluated. The PZT-Au-Si cantilever applications for both piezoelectric actuators and energy harvesters have been confirmed.

Abstract: As an energy conversion material, piezoelectric ceramic lead zirconate titanate (PZT) has been used in a wide range of areas. And a PZT wafer bonding with a silicon wafer technology is a promising method to fabricate micro-sensors and micro-actuators using well-established silicon machining techniques. In order to obtain the excellent piezoelectricity and suitable thickness from the bulk PZT, a method is presented. It is to bond a bulk PZT onto a silicon wafer via an intermediate layer. In this paper, two bonding methods are presented. One is to bond a bulk PZT with a silicon wafer by anodic bonding technique using a thin glass film as the intermediate layer. The other is to bond a bulk PZT with a silicon wafer by eutectic bonding using a thin gold film as the intermediate layer. The glass film is 2µm in thickness, deposited by sputtered method. Anodic bonding conditions are: 0.8MPa in pressure, 500 oC in temperature, 250V in voltage and different bonding time. The bonding strength test shows that the maximum bond strength is 13.93 MPa when the bonding time was 60 min. It is void-free structure in the interface of the PZT-Glass-Si structure. The gold film is 1.6µm in thickness, deposited by evaporation method. The eutectic bonding conditions are: 0.8MPa in pressure, 500 oC in temperature, and different bonding time. The bond strength of the PZT-Au-Si structure was tested and the maximum value was 13.19 MPa when the bonding time was 60 min.

Abstract: As Recently, wafer level packaging (WLP) received lots of attention in system because it shows the potential to reduce packaging cost, while the yield of devices after dicing and packaging can be increased. In this study, we newly proposed WLP for light emitted diodes (LED) using MEMS technology. Our silicon package structure is composed of base and reflector cup. The role of base is that settle LED chip at desired position and supply electrical interconnection for LED operation. Reflector cup was formed by an-isotropic wet etching. Package platform could be fabricated by eutectic bonding between base and reflector cup using AuSn. We carried out process using six sigma methodology. We first decided 2 factors and 3 levels by design of experiment (DOE). One factor is the kind of metal model. The other is the shape of pattern. It was used that three-kind metal models are Au (cup), AuSn (cup), and AuSn (base). The bonding strength is measured using a die shear strength tester. It carried out in the repetition experiment by a unit of 3 times. As a result of this test, the AuSn(base) metal model and the No.3 pattern were applied by the optimal condition. We set the value of the low limit at shear strength 950g/mm2 for applying sigma level. This value is a generally used for eutectic bonding packages. The experiment results have 3.13 sigma level (95% yield). In this paper, We show the final LED package which is finished up to LED attach, wire bonding, encapsulation, etc. This wafer level bonding process demonstrates its promising potential at the wafer level packaging in LED packaging.

Abstract: Our experiments highlight that gold-silicon eutectics are fairly influenced by the thickness of Au layer and the wastage of Si, i.e. the wasting thickness of the silicon die. In the experiments, a bonding intensity testing method, called Press-arm model, is used to verify the Au-Si eutectics bonding strength. Through the intensity value of the bonding interface, we analyze the eutectics condition of the bonding interface at different temperatures and discuss the optimum procession of the wafer capsulation.