Papers by Keyword: GOI

Abstract: In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Abstract: This paper presents Time Dependent Dielectric Breakdown (TDDB) testing of gate oxide on 0.5µm BiCMOS Technology. The gate oxide quality for the technology has been investigated and furthermore to qualify the whole set up of the foundry from the process, equipment, cleanroom control and raw material used to produce high quality gate oxide and hence good quality of BiCMOS devices. TDDB test is the most widely used testing to check the quality of gate oxide and in this paper the TDDB test done on MOS capacitors fabricated using 0.5 µm BiCMOS Technology. Seven consecutive qualification lots have been tested and the data shown that TDDB measurement is capable to differentiate between accepted wafer and rejected wafer. The data also shown that TDDB test was capable to characterise 0.5 µm BiCMOS gate oxide with higher yield and comparable with reference lot from other foundry fab.

Abstract: The impact of metal-ion contamination (present on wafer surface before oxidation) on gate oxide integrity (GOI) is well known in literature, which is not the case for clean silica particles [1, 2]. However, it is known that particles present in ultra-pure water (UPW) decrease the random yield in semiconductor manufacturing [3]. The presence of silica in UPW is common knowledge. UPW has also a certain content of metal ions, which can be attached to silica. That means, when a wafer is in contact with UPW metal ion can directly and/or in form of a silica-metal conglomerate be attached to the wafer surface. That means, it is not known in which form metal-ion contamination will deteriorate GOI the most. In order to receive more clarity in this field a short-loop study was set up, where we want distinguish between the impacts of - low metal ion contamination (Calcium), - clean silica particles (330nm) contamination, - silica particles with metal-ion core (330nm) contamination, and - metal-ion contamination at similar concentration as the metal-ion core of the particles on GOI (uniform and none uniform distribution).