Papers by Keyword: InGaAs

Abstract: The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO₂ which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.

Abstract: Indium gallium arsenide (InGaAs) is one of the candidate materials to overcome the physical limitation of Si due to its excellent electrical properties. The effect of surface oxidation on the etching characteristics of InGaAs surface in acidic solutions were investigated. InGaAs surfaces was etched in HCl/H₂O₂/H₂O (CPM) and HNO₃/H₂O₂/H₂O (NPM), while there was no thickness change in diluted HCl or HNO₃. The CPM-treated InGaAs surface had a lower etching rate than the NPM-treated one, while etching rate of oxidized layer was higher in diluted HCl than in HNO₃. NaCl added in the NPM acts as an etching inhibitor for InGaAs and the etching rate was significantly suppressed. It is thought that Cl⁻ anion inhibits the formation of hydroxyl radical (OH∙) or consumes OH∙ in acidic solution, inhibiting surface oxidation of InGaAs and suppressing its material loss.

Abstract: In this paper for the first time, the performance of Dielectric Engineered Tunnel Field Effect Transistors (DE-TFETs) is evaluated on the InGaAs channel. Two DE-TFETs based on gate-dielectric structures, namely, Device-A and Device-B are modeled and characterized for both n-type and p-type operations to attain low subthreshold slope (SS) and drain induced barrier lowering (DIBL) using La₂O₃ as high-k gate dielectric. A structural modification of Device-B is illustrated that improves the on-state current (I_on), SS, and DIBL. Then, performance of both devices are analyzed based on physical oxide thickness (T_ox). The simulation results show that the modified Device-B has the lowest SS of 15.31 mV/dec and 54.64 mV/dec, I_on/I_off ratio of ~10⁹ and ~10⁶ with off-state current (I_off) of ~10^-15 A/µm and ~10^-12 A/µm for n-DE-TFET and p-DE-TFET, respectively. Furthermore, the performance parameters of both devices are studied for digital and analog applications and it is found that the modified Device-B can be a potential candidate for future digital applications due to its low power dissipation of 13.55 µW/µm and 27.56 µW/µm for n-DE-TFET and p-DE-TFET, respectively. On the other hand, Device-A shows high transconductance (g_m) of 722.52 µS/µm and 424.3 µS/µm and cut-off frequency (f_T) of 211.95 GHz and 290.86 GHz for n-DE-TFET and p-DE-TFET, respectively, and can be a viable candidate for future low power analog applications.

Abstract: The integration of III-V and Ge materials on Si surface causes many issues with complexity such as lattice mismatch with silicon. In particular, the surface preparation and passivation of InGaAs is very challenging, because the formation of InGaAs/high-K interface is important, but not well understood. For the systematical study of InGaAs surface during wet processes, the effect of various wet etching processes on the surfaces of binary III-V compound semiconductors (GaAs, InAs, GaSb and InSb) was studied from the viewpoints of surface oxidation, material loss (dissolution), and passivation. Based on that, further effort to understand the surface reactions on ternary InGaAs compound semiconductor was made. In addition, process sequential effect on the InGaAs surface was investigated.

Abstract: In Situ gas phase passivation methods can enable new channel materials. Toward this end pure anhydrous HOOH and H2NNH2 membrane gas delivery methods were developed. Implementation led to Si-OH passivation of InGaAs(001) at 350C and Si-N-H passivation of SiGe(110) at 285C. XPS and initial electrical characterization has been carried out. Feasibility for In Situ dry surface preparation and passivation was demonstrated.

Abstract: We report the development of two epilayers namely the baseline highly strained channel and enhanced low gate leakage samples. The Hall data shows that the enhanced epilayer portraying higher sheet carrier concentration, but comparable carrier mobility in the 2-DEG layer, as compared to the baseline sample. The WinGreen simulation also conformed the enhanced epilayer advantages where wider Schottky barrier is observed and subsequently double carrier concentration is simulated in the channel. Both samples show low AuGe/Au Ohmic contact resistivity of approximately 0.16 Ω.mm. A tremendous advantage on 1 μm Schottky gate leakage is also recorded on enhanced epilayer where the leakage is more than seven times lower than that of the baseline sample. The resulted characteristics are much better than the reported submicron device, thus this device has find an important application in high-gain lossless transmission, especially in underwater optical communication system.

Abstract: InGaAs nanoflowers have been prepared on InP substrates by MOCVD, using TMIn, TMGa and AsH3 as reactive precursors at 420 oC. Through observation by scanning electron microscopy, we find that InGaAs nanoflowers are composed with blades and rods. The flower patterns are controlled by the growth temperature. The nanoflowers of InGaAs are disappeared, when we alter the growth temperature up and down. The InGaAs nanoflowers are In0.98Ga0.02As.

Abstract: The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs and high mobility substrates, including compound semiconductors (III-V). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under low thermal budget environments for III-V materials. Ion implantation into III-V materials presents a problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. This paper presents a potentially defect-free alternative, mono-layer doping (MLD), which utilizes wet processing techniques.

Abstract: In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.

Abstract: The megasonic cleaning efficiency is evaluated as a function of the angle of incidence of acoustic waves on a Si wafer. Acoustic Schlichting streaming alone is not able to remove nanoparticles smaller than 400 nm. It is shown that oscillating or collapsing behavior of bubbles are responsible for removing nanoparticles smaller than 400 nm during a cleaning process with ultrasound. Optimal particle removal efficiency is obtained around the angle of acoustic transmission of the silicon wafer.