Papers by Keyword: Low K

Abstract: The purpose of this paper is to study the effects of wet strip clean for metal void reduction in trench first metal hard mask back end of line (BEOL) integration process in 14 nm Technology. A thicker TiN film is becoming important to resolve via-metal short yield and time-dependent dielectric breakdown (TDDB) issues caused by the Litho-Etch-Litho-Etch (LELE) misalignment due to smaller patterning features. This brings the multitude of advanced integration technology need for complete TiN hard mask (HM) removal, post etch residue removal, ultra low-k dielectric (ULK) and Cu stability, interconnect resistance, and continuing high volume manufacturing (HVM) cost challenges together with environmental concerns and the waste handling/treatment cost. At GlobalFoundries, we achieved a wet strip clean process with a 45 % lower cost of ownership (CoO) while maintaining the TiN HM removal rate, baseline critical dimension (CD), normalized defect density (DOI), the ULK and Cu stability, via resistance, and yield.

Abstract: In our study, the dielectric properties of SiOC low k thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. A SiOC low k thin film was fabricated onto a n-type silicon wafer by dip coating using 30wt % polyphenylcarbosilane in cyclohexane. Curing of the film was performed in air at 300°C for 2h. The thickness of the film ranges from 1 μm to 1.7 μm. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and shows a dielectric constant as low as 3.26 without porosity added. The SiOC low k thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.