Papers by Keyword: Photoresist Strip

Abstract: Batch SPM systems do not meet the current clean specification/requirements below 28nm. Single wafer SPM systems use a high volume of chemistry which runs to drain, while meeting the cleaning specifications below 28nm. The work in this paper describe the use of a batch SPM system and a single wafer clean in an integrated system, Ultra-C Tahoe which results in meeting the technical specification and using less that 80% of the SPM chemistry used in single wafer systems. The data collected shows this new system meet the specifications, whilst saving more than 80%of SPM chemistry.

Abstract: As the semiconductor device technology is moving toward increasingly smaller nodes, it is becoming more challenging to keep the wafers free from contamination of even smaller particles. Wet cleaning process takes a major role in keeping the wafers clean, especially in post-RIE cleans. However, as every other process, wet cleaning also contributes some defects as adders which can potentially cause significant yield killer defects. A cluster of defects, classified as incomplete etch, was observed at the center of the wafer with a wet clean recipe (CIP1) since the adders from this recipe were not allowing the etch process and rendering incomplete etch defects. In this work, we optimized this CIP1 recipe to eliminate defects with the bull’s eye signature at the wafer center and widened the process window of this type of wet cleaning process. The new recipe (CIP2) showed 100% success rate while CIP1 recipe had an occurrence of 35% failure for the bull’s eye signature on the similar quality and quantity of wafers.

Abstract: In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.

Abstract: The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.