Papers by Keyword: Plasma Etch

Abstract: Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, while I-V characterization of fabricated trench MOS-capacitor devices demonstrate the influence of trench base corner rounding on gate oxide breakdown.

Abstract: Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.