Authors: Shu Bin Yan, Xiao Qian Wang, Ke Zhen Ma, An Fu Zhang, Chen Yang Xue, Wen Dong Zhang
Abstract: In the paper, it demonstrates highly integrated tenth-order filters in silicon-on-insulator (SOI). The micro-ring resonators have a small radius of 5μm and a very large free spectral range ~ 18nm at 1.55μm communication band. For through port responses, the grating and the high-order optic filters with ten coupled micro-ring resonators are designed and demonstrated, and grating responding well matches with the experiment resonators. Devices are patterned with electron-beam lithography (EBL). And 2μm SiO2 layer is covered on the silicon waveguide, thus reducing the propagation loss in micro-ring resonators.
991
Authors: Chao Liu, Chen Yang Xue, Dan Feng Cui, Jun Bin Zang, Yong Hua Wang, Jing Xue Wang
Abstract: We designed High-Q micro-ring resonators based on SOI material. A new method of using a top SiO2 layer to cover the waveguide is applied and the tested Q factor is as high as 1.0135×104. Micro-ring resonator has been fabricated using Electron-Beam Lithography and Inductive Coupled Plasma. OptiFDTD was used to simulate the micro-ring resonator and we compared the transmission spectrum of this resonator with the resonator without SiO2 covering.
443
Authors: Ke Zhao, Xiao Min Lei, Guo Feng Xie, Wen Hua Xiong
Abstract: Based on a silicon-on-insulator (Silicon-on-insulator, SOI) material system design and optimization of a high performance, the polarization independent of 1 × 3 subwavelength grating stars beam splitter. By a rigorous coupled-wave analysis method showed that, in the 1550nm wavelength range, at vertical incidence, the device on the transverse electric field (transverse electric, TE) ,the 0 and ± 1 order transmittance is 31%, 32%, 32%,respectively; cross the magnetic field (transverse magnetic, TM), the 0 and ± 1 transmittance is 33%, 32%, 32%, respectively.
481
Authors: Kun Bo Wang, Li Shuang Feng, Zheng Fang Dong
Abstract: In order to realize the opto-electronic integration of optic gyro, the quasi-planar ridge SOI waveguide resonator is proposed due to its low loss and small bend radius. First, the single mode condition and smallest bend radius were simulated by using the 3-dimension finite difference beam propagation method (3-D BPM). Then the relationship between the sensitivity of gyro and the resonator characteristics, such as radius and coupling coefficient, was analyzed by applying the model of the integrated optical gyro. Based on these simulations, the ridge height and width of the waveguide were 220 nm and 1.2 μm respectively and the smallest bend radius was 600μm. It is shown that the theoretical detection limit of the gyro was 0.031 °/s when the resonator diameter was 5cm and the couplers splitting ratio was 46.7:53.3. This gyro system is suitable for tactical and civil applications.
424
Authors: Don Dussault, F. Fournel, V. Dragoi
Abstract: Current work describes development, testing and verification of a single wafer megasonic cleaning method utilizing a transducer design that meets the extreme particle neutrality, Particle Removal Efficiency (PRE), and repeatability requirements of production scale wafer bonding and other applications requiring extremely low particle levels.
269
Authors: Wei He, Zheng Xuan Zhang
Abstract: A new approach to model the total ionizing dose (TID) induced back channel threshold voltage shift in SOI NMOS transistors was presented. Using a 2D finite element simulation, the trapped charge density in the buried oxide of SOI NMOS resulting from irradiating was analyzed. The model derives from the Radiation-Induced parasitic MOSFET created at the back of the buried oxide . A comparison of the theoretical and experimental results have been obtained for different radiation doses.The agreement between experimental and simulated curves is excellent.
2243
Authors: K. Senthil Kumar, Saptarsi Ghosh, Anup Sarkar, S. Bhattacharya, Subir Kumar Sarkar
Abstract: With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.
5150
Authors: Jalal Jomaah, Majida Fadlallah, Gérard Ghibaudo
Abstract: A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are illustrated through experimental data obtained on advanced CMOS generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown.
441
Authors: Jalal Jomaah, Majida Fadlallah, Gérard Ghibaudo
Abstract: A review of recent results concerning the DC characterization of FD- and Double Gate SOI MOSFET’s and FinFETs in modern CMOS technologies is given. By proper extraction techniques, distinction between the different interaction mechanisms is done. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is directly impacted by shrinking the gate length in sub 100nm architectures.
407
Authors: Dan Feng Cui, Chen Yang Xue, Xiao Gang Tong, Yu Jian Jin, Wen Dong Zhang
Abstract: In this paper, we discuss the theory research and testing methods of a grating coupler. The grating coupling efficiency of parameters and the corresponding theoretical simulation was studied systematically. Meanwhile, the coupling efficiency in theory can be improved to 76% using an optimized grating design. The fabrication of the couplers in silicon-on-insulator is focusing on ion beam method (FIB). Using the tunable NewFocus laser with an adjustable extent of 1520~1570nm as the sources, Si waveguide grating is achieved vertical coupler through coupling a single-mode fiber with the diameter of 10.4. In the experiment, when the input wavelength is 1550nm, the maximum coupling efficiency is measured approximately 31% and 1 dB bandwidth is approximately 30 nm.
711