Papers by Keyword: Self-Aligned

Abstract: The SiC trench gate MOSFET with narrow cell pitch is demonstrated using a process in which the n⁺ source is self-aligned to the trench gate. A minimum cell pitch of 1.6 μm, which is difficult to achieve using the conventional device structure, is easily fabricated by applying a deep n⁺ source and a buried interlayer dielectric structure. The cell pitch reduction indicates a beneficial trend that contributes to a decrease in the specific on-resistance and an increase in the breakdown voltage. The process and structure are promising for further improving SiC power device characteristics.

Abstract: Silicon Carbide (SiC) power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from theoretical limits of performance. Above ~1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and the JFET regions. Trench MOSFETs generally have smaller cell area than planar DMOSFETs and are inherently more scalable. In this paper, we describe a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs.”

Abstract: Because of difficulty in deep ion implantation, the recessed gate structure has been favored in SiC SIT. In order to improve the frequency, it is a good method to decrease the gate length by eliminating the side wall ion implantation affection. We developed normally-on RF 4H-SiC SIT with high small signal gain. The effect of forming the side wall protection between the source mesa and the gate area was simulated