Papers by Keyword: Shockley Stacking Faults

Abstract: We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a semi-sacrificial basal plane dislocation (BPD) conversion epilayer, polishing away a portion of that conversion epilayer to recover a smooth surface and then growing the device epilayers following specific methods to prevent the reintroduction of BPDs. With our best processing, we achieve a BPD density of < 10 cm-2 and an extended defect density of < 1.5 cm-2. Specifics of low BPD processing and particular concerns and metrics will be discussed in regard to process optimization and simplification.

Abstract: We provide evidence of shrinking of Shockley-type stacking faults (SSFs) in the SiC epitaxial layer by high temperature annealing. Photoluminescence (PL) mapping in combination with high-power laser irradiation makes it possible to investigate the formation of SSFs, which lie between a pair of partial dislocations formed by dissociation of a basal plane dislocation (BPD), without fabrication of pin diodes. Using this technique, we investigated the annealing effect on SSFs. Comparing before and after annealing at 600°C for 10 min, it became obvious that high-temperature annealing results in shrinking of the faulted area of the SSFs. The SSFs form into the same features as those before annealing when high-power laser irradiation is performed again on the same area. This result shows that the faulted area of SSFs shrinks by 600°C annealing but the nuclei of SSFs (BPDs) do not disappear.

Abstract: Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.