Papers by Keyword: Wet Etch

Abstract: Advance nanoscale patterning technology requires high resolution lithography, from ultraviolet (UV, i-line system) to deep ultraviolet (DUV, KrF system) until extreme ultraviolet (EUV), but the compatibility study of new resist types and wet etchant is lacking. The compatibility is defined as the duration of a photoresist being able to withstand in wet oxide etchant. Poor compatibility has potential resist lifting and/or penetration during wet etch process, which causes electronic device performance drifting. Currently, wet oxide etching is widely used in the gate oxide wet etch using patterned resist, as well as in the backside oxide removal with blanket resist front-side coverage. In this paper, we explore the compatibility and understand the impact factors, based on commonly used resist (i.e., KrF and i-line system resist) and wet etch chemicals (i.e. HF based etchant) in industry. It is important to do a quick and straightforward compatibility check before we implement new resists on actual product wafers, to prevent poor compatibility caused resist lifting and/or penetration during wet etch process. Based on oxide thickness check and resist lifting phenomena, it is found that resist baking condition, resist polymer type, resist composition, and lag time from resist coating to wet oxide etching all will affect the compatibility between HF based etchant and resist.

Abstract: In this work, we characterized the wet chemical atomic layer etching of an InGaAs surface by using various surface analysis methods. For this etching process, H₂O₂ was used to create a self-limiting oxide layer. Oxide removal was studied for both HCl and NH₄OH solutions. Less In oxide tended to remain after the HCl treatment than after the NH₄OH treatment, so the combination of H₂O₂ and HCl is suitable for wet chemical atomic layer etching. In addition, we found that repetition of this etching process does not impact on the oxide amount, surface roughness, and interface state density. Thus, nanoscale etching of InGaAs with no impact on the surface condition is possible with this method.

Abstract: The semiconductor industry is undergoing a transition driven by end use markets. In recent years, mobile devices have been the leading generator of growth. Now the connection of various products and machines to the internet is generating new and extensive demands for memory (storage of the data), logic (intelligent processing of the data including machine learning), and sensing (e.g., image sensors generating visual data). Thus the versatile planar MOS transistor based semiconductor technology has diverged into various specialized and complex branches, with each technology type using unique approaches to address scaling challenges. These lead to specific requirements for semiconductor wafer surface preparation. This paper will review the high level industry trends and how they affect surface preparation specifically.

Abstract: Sub-10 nm technology node manufacturing processes may require the use of thicker and denser TiN hard mask for patterning at the BEOL. The modified TiN, which tends to be more chemically robust, must be removed using a wet etch process, while maintaining typical throughput - no extension of typical wet etch process times. To satisfy these needs, a new TiN etching accelerator was found that enhanced the activity of peroxide-related species in a wet etch chemical formulation that achieved increased TiN etch rate relative to formulation without TiN etch rate accelerator (Sample 1), while also minimizing the damage to ultra-low-k inter layer dielectric (ILD) layer by a strong base, also present in the formulation. We report here the result of a solvent based formulation, which adopted the TiN etching accelerator. The formulation was able to maintain TiN etch rate and remove post-etch residue, while remaining selective to ultra-low-k ILD, Co and Cu. The TiN etch rate of the accelerator enhanced formulation can be further tuned by modifying the process temperature or the hydrogen peroxide to formulation mixing ratio and has the potential capability to process > 400 wafers.

Abstract: Beginning at the 45nm node, the semiconductor industry is moving to high-k gate dielectrics and metal gate electrodes for CMOS logic devices [. Although different approaches of building these devices are being pursued, most of the industry has consolidated behind a gate last approach, in which the transistor is built around a dummy poly polysilicon gate, which is subsequently removed and replaced with a metal gate. Current approaches to removing the dummy poly gate include plasma-based dry processes and liquid-phase wet etching.

Abstract: 3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.