Papers by Author: Carlo Waldfried

Abstract: The removal of ion implanted photoresist (II-PR) after implantation of ultra shallow extension and halo regions is considered as one of the most challenging front-end-of-line (FEOL) processing steps for 32nm and beyond CMOS technology nodes. Commonly used resist strip processes such as fluorine-based dry plasma ash and hot sulfuric/peroxide mixtures induce unacceptable levels of oxidation and material loss [1-.

Abstract: Two alternative plasma strip processes were developed to meet the photoresist (PR) removal requirements of future technology nodes. Compared to traditional oxidizing chemistries, the new plasma strip approaches showed significantly lower silicon oxidation and substrate loss, while achieving good residue removal capabilities. Plasma strip-induced dopant loss and profile changes were also evaluated for gate-first and gate-last high-k/metal gate applications.

Abstract: The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.

Abstract: High dose, ultra shallow junction implant resist strip requires minimal substrate loss and dopant loss. Silicon recess (silicon loss) under the source/drain (S/D) extensions increases the S/D extension resistance and decreases drive currents by changing the junction profile. ITRS surface preparation technology roadmap [1] targets silicon loss to be 0.4Å per cleaning step for 45nm and 0.3Å for 32nm generation. Fluorine-containing chemistries which are often used to enhance implanted resist strip and residue removal result in unacceptable substrate loss. A non-fluorine plasma strip was developed in earlier work and is qualified for 45nm logic production [2]. The objective of this work is to study the substrate damage that is induced by the resist strip plasma process. Silicon surface oxidation and silicon loss of different plasma strip chemistries were evaluated with various metrologies such as optical ellipsometry, electrical oxide measurement, XPS, TEM and mass measurement. The impact of different strip chemistries on dopant retention and distribution is also discussed.