Papers by Author: Heiner Ryssel

Abstract: One challenge for volume manufacturing of 4H-SiC devices is the state-of-the-art wafer dicing technology – the mechanical blade dicing which suffers from high tool wear and low feed rates. In this paper we discuss Thermal Laser Separation (TLS) as a novel dicing technology for large scale production of SiC devices. We compare the latest TLS experimental data resulting from fully processed 4H-SiC wafers with results obtained by mechanical dicing technology. Especially typical product relevant features like process control monitoring (PCM) structures and backside metallization, quality of diced SiC-devices as well as productivity are considered. It could be shown that with feed rates up to two orders of magnitude higher than state-of-the-art, no tool wear and high quality of diced chips, TLS has a very promising potential to fulfill the demands of volume manufacturing of 4H-SiC devices.

Abstract: In this work, we investigate the impact of Al-implantation into n-MOSFET channel regions together with its p-doping concentration upon the mobility limiting scattering mechanisms in the channel. For this purpose, a study of the interface trap density, interface trapped charge density, field-effect mobility, and Hall mobility is carried out for normally-off n-MOSFETs with different doping profiles and concentrations in the channel region. The trend of the field-effect and the Hall mobility as well as the differences thereof will be discussed. Based on the determined mobilities in the range from 11.9 cm²/Vs to 92.4 cm²/Vs, it will be shown that for p-doping concentrations above 5·10¹⁶ cm^-3 Coulomb scattering is the dominant scattering mechanism for both, low- and high-field mobility. In contrast, for p-doping concentrations below 5·10¹⁶, cm^-3 further scattering mechanisms will be considered that may account for the observed mobility trend at high electric fields.

Abstract: N-LDMOS and n-LIGBT structures were manufactured with the same dimensions on a 4H-SiC wafer in order to allow for a direct comparison. The comparison of the devices includes output and transfer characteristics, blocking characteristics, and temperature behavior.

Abstract: To study mobility limiting mechanisms in (0001) 4H-SiC, lateral n-channel MOSFETs in p-implanted wells on n-type epitaxial layers were manufactured and additionally selectively shallow implanted with different nitrogen (N) doses in the channel region. The mobility was found to be limited by Columbic scattering at low electric fields. Further surface roughness scattering was con-sidered as a possible mobility degradation mechanism at high electric fields. First investigations of the SiC surface by atomic force microscopy (AFM) in the channel region after implantation, anneal-ing, and gate oxide removal revealed a rather rough topology. This could lead to fluctuations in the surface potential at the SiC/SiO2 interface, thus accounting in part for surface roughness scattering.

Abstract: N-channel MOSFETs were manufactured on p-type and on p-implanted, n-type 4H-SiC substrates. The electron mobility in the inversion channel was measured to be correlated with the structural and chemical properties determined by transmission electron microscopy. With regard to what was previously discussed in the literature, interfacial layer formation and carbon distribution across the SiC/SiO2 interface were considered in relation with the measured Hall electron mobility.

Abstract: The suitability of normally-off 4H-SiC MOSFETs for high temperature operation in logic gates is investigated. Fowler-Nordheim analysis shows a lowering of the effective tunneling barrier height at elevated temperatures. Trap assisted tunneling induced by carbon interstitials is proposed as the responsible mechanism. Nevertheless, reliability of MOS devices even at 400°C is excellent with an extrapolated critical field of 2.69MV/cm for a 10 year time to dielectric breakdown. The switching behavior of logic gates is also characterized between 25°C and 400°C. Using these logic gates, a fully integrated edge triggered flip-flop is build and high temperature operation is demonstrated.

Abstract: Metal-oxide-semiconductor (MOS) capacitors were formed on 4H-silicon carbide (SiC) using thermally grown silicon dioxide (SiO2) as gate dielectrics, both with and without nitrogen incorporation within the oxide. The field dependence of the charge trapping properties of these structures was analyzed and linked to the observed Fowler-Nordheim current degradation. Furthermore, first considerations were presented that indicate an electron impact emission induced generation of positive oxide trapped charge.

Abstract: Normally-off 4H-SiC MOSFETs are used to build NMOS logic gates intended for high temperature operation. The logic gates are characterized between 25°C and 500°C. Stable gate operation for more than 200h at 400°C in air is demonstrated. The excellent MOS reliability is quantified using I-V curves to dielectric breakdown and constant voltage stress to breakdown at 400°C. Although the effective tunneling barrier height B for electrons lowers to 2eV at 400°C, the extrapolated lifetime from constant voltage stress to breakdown measurements is longer than 105h at 400°C for typical logic gate operating field strength of 2MV/cm.

Abstract: The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

Abstract: In this work, the electrical characteristics and the reliability of 80nm thick deposited oxides annealed in NO and N2O on the 4H-SiC Si-face for gate oxide application in MOS devices is analyzed by C-V, I-V measurements and by constant current stress. Compared to thermally grown oxides, the deposited oxides annealed in N2O or NO showed improved electrical properties. Dit-values lower than 1011cm-2eV-1 have been achieved for the NO sample. The intrinsic QBD-values of deposited and annealed oxides are one order of magnitudes higher than the highest values reported for thermally grown oxides. Also MOSFETS were fabricated with a channel mobility of 20.05 cm2/Vs for the NO annealed deposited oxide. Furthermore annealing in NO is preferred to annealing in N2O regarding µFE- and QBD-values.