Papers by Author: Hirokatsu Yashiro

Abstract: In this paper, we present the formation of extended epitaxial defects, such as carrot defects, from threading screw dislocations (TSDs) with a morphological feature at the surface of the substrates. It was confirmed using highly sensitive surface observation, atomic force microscopy (AFM) and KOH etching that the surface roughness around a TSD was observed as the morphological feature and TSDs with such a morphological feature formed extended epitaxial defects with high frequency of appearance compared to usual TSDs without any features. The density of TSDs with such morphological feature depended on the polishing methods. Furthermore, we observed that the formation and shapes of extended defects from TSDs with such morphological feature were affected by step-bunching at the surface of the epilayers.

Abstract: A possible mechanism of hexagonal void movement during Physical vapor transport (PVT)-growth is proposed in terms of quasi-equilibrium phase transition process based upon the Si-C binary phase diagram. The hexagonal void movement can be realized when two different reactions occurs simultaneously: (1) SiC(s) solidification and (2) decomposition without graphitization. Further, the kinetic instability of the void movement observed is also discussed, and found to be explainable if the effect of the temperature gradient existing in the crystal grown in conventional PVT-process is included.

Abstract: 4H-SiC epitaxial growth on 2˚ off-axis substrates using trichlorosilane (TCS) is presented. Good surface morphology was obtained for epilayers with C/Si ratios of 0.6 and 0.8 at a growth temperature of 1600°C. The triangle defect density was reduced to a level below 5 cm^-2 at 1600°C and below 1 cm^-2 at 1625°C for a C/Si ratio of 0.8. Photoluminescence (PL) measurements were carried out with band-pass filters of 420 nm, 460 nm, and 480 nm to detect stacking faults. A stacking fault density of below 5 cm^-2 was achieved at 1600°C and 1625°C with a C/Si ratio of 0.8. The optimal conditions for TCS growth were a C/Si ratio of 0.8 and a growth temperature of 1600°C. The evaluation of stacking faults and etch pit density indicated that the use of 2˚ off-axis substrates and TCS is effective for reducing basal plane dislocations. Comparing these results to those using silane (SiH₄) with HCl added, it was demonstrated that TCS is much more suitable for obtaining high-quality epilayers on 2º off-axis substrates.

Abstract: Structures and propagating behaviors of threading dislocations (TDs) in PVT-grown 4H-SiC single crystals were both investigated using Synchrotron monochromatic X-ray topography. Comparative studies by examining images obtained for the crystals with different diffraction geometries of (0004) and (11-20) of 4H-SiC revealed that a large amount of TDs are likely to be mixed in character, i.e., dislocations with Burgers vector components of both <0004> and <11-20>. Closer observations of topography images has revealed that, although TDs lie largely along the c-axis direction, some of the TDs show quite a complex propagating behavior: not extending in a straight line but meandering along the growth direction.

Abstract: Time-dependent evolutions of single and quadruple Shockley stacking faults (sSSF and 4SSF) in 4° off 4H-SiC epitaxial layers have been investigated. UV illuminations using an Hg-Xe lamp light source generate dissociations of basal plane dislocations (BPDs) into sSSFs whereas for 4SSFs no significant changes in shape occur. Detailed analyses of Photo-luminescence (PL) signals suggest that Si- and C-core partials have different PL spectrum distributions in the wavelength range larger than 750 nm, giving rise to images with different contrasts in PL mappings.

Abstract: Dislocations in highly nitrogen-doped (N > 1×1019 cm-3) low-resistivity ( < 10 mcm) 4H-SiC substrates were investigated by photoluminescence imaging, synchrotron X-ray topography, and defect selective etching using molten KOH. The behavior of dislocations is discussed particularly in terms of their glide motion in the presence of a high concentration of nitrogen. The results indicate that nitrogen impurities up to mid 1019 cm-3 concentration do not show any discernible influence on the glide behavior of basal plane dislocations (BPDs) in 4H-SiC crystals grown by physical vapor transport (PVT) method.

Abstract: The epitaxial growth process was optimized in order to obtain good surface morphology for epilayers grown on 4˚ off-axis substrates. The optimization was carried out from growth temperatures and gas chemistry including C/Si ratio. Step-bunching was significantly suppressed by the optimized process and a surface roughness Ra of 0.2 nm was achieved. Etch pit density evaluation by KOH etching indicated that the basal plane dislocations were reduced to less than 50 cm-2 by the use of 4˚ off-axis substrates. Photoluminescence evaluation showed that the epilayer grown by the optimized process had a better crystalline quality than that grown by a standard process. Schottky diodes fabricated on the epilayer by the optimized process represented the ideality factor n of 1.01 and the barrier height of 1.67eV. These results demonstrate that high quality epilayers with smooth surfaces comparable to those on 8˚off-axis substrates were obtained on 4˚off-axis substrates.

Abstract: In-grown type stacking faults (SFs) like structures were observed in 100mm diameter 4H-SiC crystals by Photoluminescence (PL) mappings, and structural analyses using HRTEM clarified that the SF-like structures were comprised of 6H (3, 3) stacking sequences. The stacking sequences of the SF-like structures observed are different from the SFs formed in the a-face grown crystals, suggesting that it is due to 6H nucleation on {0001} plane terraces.

Abstract: The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.

Abstract: The stacking fault formation in highly nitrogen-doped n+ 4H-SiC single crystal substrates during high temperature treatment has been investigated in terms of the surface preparation conditions of substrates. Substrates with a relatively large surface roughness showed a resistivity increase after annealing at 1100°C, which was confirmed to be caused by the formation and expansion of double Shockley-type basal plane stacking faults in the substrates. The occurrence of the stacking faults largely depended on the surface preparation conditions of the substrates, which indicates that the primary nucleation sites of stacking faults exist in the near-surface regions of substrates. In this regard, mechano-chemically polished (MCP) substrates with a minimum surface roughness (< 0.3 nm) exhibited no resistivity increase and very few stacking faults after annealing even when the nitrogen concentration of the substrates exceeded 1×1019 cm-3.