Papers by Author: Kuniaki Yagi

Abstract: We carry out ab initio density functional theory calculations to investigate the fundamental mechanical properties of stacking faults in 3C-SiC, including the effect of stress and doping atoms (substitution of C by N or Si). Stress induced by stacking fault (SF) formation is quantitatively evaluated. Extrinsic SFs containing double and triple SiC layers are found to be slightly more stable than the single-layer extrinsic SF, supporting experimental observation. Effect of tensile or compressive stress on SF energies is found to be marginal. Neglecting the effect of local strain induced by doping, N doping around an SF obviously increase the SF formation energy, while SFs seem to be easily formed in Si-rich SiC.

Abstract: A reliable method for reducing the stacking faults (SFs) is demonstrated on the 3C-SiC (001) surface. It is a practical method based on Monte Carlo (MC) simulations of SF propagation during 3C-SiC epitaxial growth, which showed that introducing some discontinuity on the (001) surface enhanced SF reduction. The method is implemented by patterning on the 3C-SiC (001) surface and subsequent homo-epitaxial growth, and this sufficiently reduced the SF density to less than 400 cm^-1. A yield of 97.4 % was estimated for a device-ready area of 10 mm² by statistical measurements of SF density on the entire epitaxial layer surface.

Abstract: Technique of bulk-like 3C-SiC film (up to 300 µm) growth on undulant-Si substrate is known to be very effective to reduce stacking fault density as well as that of other planar defects. However, freestanding 3C-SiC wafer shows anisotropic warpage involving large convex curvature in the direction perpendicular to the ridge of undulation ([110] direction), and slight concave curvature in parallel direction ([-110] direction), i.e. saddle shape. In this paper the origin of the warpage of the 3C-SiC wafer is investigated. Ex-situ curvature measurements and stress calculation reveal that large compressive intrinsic stress is generated during high-temperature growth process (1623 K) in both parallel and perpendicular directions. In order to investigate the intrinsic stress distribution along the [001] direction, a reactive ion etching (RIE) is conducted for the 3C-SiC on Si substrate to observe the dependence of the SiC/Si system curvature as a function of 3C-SiC thickness. This observation shows that the intrinsic stress component perpendicular to the ridge of undulation presents nonuniform distribution in [001] direction. The remarkable change in the intrinsic stress is observed in the 50 µm-thick region from SiC/Si interface. A finite element method simulation using the obtained intrinsic stress distribution clearly explains that the anisotropic warpage of SiC wafer is induced by the intrinsic stress distribution in quantitative manner. Microstructure change induced by stacking fault reduction process (stacking fault collision) would be the cause of the intrinsic stress variation.

Abstract: Quantitative efficacies of several methods for stacking fault (SF) reduction are evaluated using Monte Carlo (MC) simulation. SF density on a 3C–SiC {001} surface depends on interactions of adjoining SFs: annihilation between counter pairs of SFs and termination by orthogonal SF pairs. However, SFs are not entirely eliminated when growth occurs on undulant-Si and switch back epitaxy (SBE) due to spontaneous SF collimation that suppresses the annihilation probability of counter SFs. The MC simulation also reveals the efficacy of SF reduction method which includes the growth of 3C–SiC on finite area bounded by side walls. One can theoretically reduce the SF density below 100 cm^-1 on 3C–SiC {001} surface. A practical way for eliminating the SF by termination at side walls is demonstrated, and it clearly exhibits that the SF density can be reduced under 120 cm^-1.

Abstract: The dependence of the reverse current of 3C-SiC p+-n diodes on the temperature and on the reverse bias is measured and a model based on thermally-assisted tunneling is proposed to explain the dominating mechanism responsible for the leakage current. Taking into account an additional ohmic shunt resistance, the experimental reverse characteristics and thermal barrier heights B can sufficiently be reproduced.

Abstract: To quantitatively evaluate the efficacy of stacking fault (SF) reduction methods, Monte Carlo simulations are carried out to reveal the SF distribution on a 3C–SiC (001) surface. SF density decreases with increasing epitaxial layer thickness and reducing size of the substrates. Additionally, SF density depends on interactions between adjoining SFs: annihilation of counter SF-pairs or termination of orthogonal SF-pairs. However, the SF is not entirely eliminated when growth occurs on undulant-Si or switchback epitaxy due to “spontaneous SF collimation”. The simulation shows that effective SF reduction methods, those that enhance the SF termination or annihilation, can theoretically attain the SF density on 3C–SiC (001) below 100 cm-1.

Abstract: p-type 3C-SiC samples were implanted by iron (Fe) and investigated by means of deep level transient spectroscopy (DLTS). Corresponding argon (Ar) profiles with similar implantation damage were implanted in order to distinguish between iron-related defects and defects caused by implantation damage. Two donor-like iron-related centers were identified in p-type 3C-SiC.

Abstract: A large leakage current (IR) is observed at reverse bias (VR) in 3C-SiC p+-n diodes. This leakage current is caused by a high density of stacking faults (SFs). The temperature dependence of IR is studied in the temperature range from 100 K to 295 K. It turns out that IR is thermally activated for reverse voltages VR  |170| V. We propose that within this voltage range IR originates from thermally assisted tunneling of electrons and holes from band-like states of the SFs into the conduction and valence band. For VR > |170| V, the thermal barrier is strongly reduced and direct tunneling dominates. These dependences are simulated in the framework of a simplified model.

Abstract: The correlation between leakage current and stacking fault (SF) density in p-n diodes fabricated on 3C-SiC homo-epitaxial layer is investigated. The leakage current density at reverse bias strongly depends on the SF density; an increase of one order of magnitude in the SF density enhances the leakage current by five orders of magnitude at a reverse bias of 400 V. In order to obtain commercially suitable MOSFETs with 10-4Acm-2 at 600V, the SF density has to be reduced below 6×104 cm-2. Photoemission caused by hot electrons, which travel along a leakage path, can be observed at the crossing between a SF and the edge of p-well region; where the maximum electric field is induced. The mechanism of the leakage current is discussed in detail in a separate paper.

Abstract: In 3C-SiC MOSFETs, planar defects like anti-phase boundaries (APBs) and stacking-faults (SFs) reduce the breakdown voltage and induce leakage current. Although the planar defect density can be reduced by growing 3C-SiC on undulant-Si substrate, specific type of SFs, which expose the Si-face, remains on the (001) surface. Those SFs increase the leakage current in devices made with 3C-SiC. In order to eliminate the residual SFs, an advanced SF reduction method involving polarity conversion and homo-epitaxial growth was developed. This method is called switch-back epitaxy (SBE) and consists of the conversion of the SF surface polarity from Si-face to C-face and following homo-epitaxial growth. The reduction of the SF density in SBE 3C-SiC results in a tremendous improvement of the device performance. The combination of the achieved blocking voltage with the demonstrated high current capability indicates the potential of 3C-SiC vertical MOSFETs for high and medium power electronic applications such as electric and hybrid electric vehicle (EV/HEV) motor drives.