Papers by Author: Masakatsu Hoshi

Abstract: We previously reported a unipolar mode p⁺-polycrystalline silicon (poly-Si)/4H-SiC heterojunction diode (SiC-HJD) [1-3]. In this work, we demonstrate a poly-Si/GaN vertical unipolar heterojunction diode (GaN-HJD) based on numerical simulation and experimental results. The GaN-HJD is expected to control the electrical characteristics of both Schottky action with a p-type poly-Si and ohmic action with an n-type poly-Si. We investigated the detailed physics of the GaN-HJD between p⁺ Si and n⁺ Si by numerical simulation. The GaN-HJD was also fabricated with p⁺-type polycrystalline silicon on an n^--type epitaxial layer on bulk GaN substrates. The measured barrier height of the GaN-HJD was 0.79 eV and the ideality factor was 1.10.

Abstract: We demonstrate a SiC trench MOSFET with an integrated low Von unipolar heterojunction diode (MOSHJD). A region of the heterojunction diode (HJD) was fabricated in a trench with p⁺-type poly-crystalline silicon on an n^--type epitaxial layer of 4H-SiC. The measured on-resistance (R_on) of the transistor action was 15 mΩcm². The measured V_on of the diode action was 2.2 V at a forward current density of 100 A/cm². The fabrication process of the MOSHJD is simple. First, the trenches of the MOSFET region and the HJD region are formed simultaneously; then poly-crystalline silicon is deposited to form the gate electrode of the MOSFET region and the anode electrode of the HJD region at the same time.

Abstract: We experimentally investigated a method of controlling the energy barrier height (ΦB) of polycrystalline silicon (poly-Si)/4H-SiC heterojunction diodes (HJDs) and conducted a numerical simulation of a novel low Von and low reverse recovery current diode using ΦB control. The ΦB of the HJD with arsenic-doped n+-poly-Si was 0.79 eV and that of the HJD with boron-doped p+-poly-Si was 1.59 eV. The ΦB can be controlled over a wide range by varying the dopant and ion implantation dose of poly-Si. A novel merged HJD (M-HJD) with two different ΦB values obtained by using ΦB control is also presented. The numerical simulation results show that the M-HJD reduces Von without increasing reverse leakage current at high reverse voltage.

Abstract: It was experimentally shown that an ONO gate dielectric carefully formed on 4H-SiC has extremely high reliability even under a negative electric field at least up to a junction temperature of 300°C, making it promising for power MOS and CMOS applications. Medium charge to failure of –30 C/cm2 was achieved for fully processed polycrystalline Si gate MONOS capacitors with an equivalent SiO2 thickness of teq = 44 nm and a 200-μm diameter. The medium time to failure of these capacitors projected for –3 MV/cm exceeds 86 and 6.3 thousand years at room temperature and 300°C, respectively. A parasitic memory action did not appear even when Eox of -6.6 MV/cm was applied for 5000 seconds.

Abstract: This paper discusses critical reliability issues and their countermeasures for vertically structured poly-Si gate n-channel power MOSFETs (DMOS) on 4H-SiC when operated at an elevated temperature of more than 300°C for a long period of time. Two destructive failures were identified in a storage life test at 500°C: a short-circuit between the source and the gate and a disconnection at the n+ source contact. The former was caused by interlayer dielectric erosion and/or Al spearing into the poly-Si gate; the latter was caused by the disappearance of the NiSix contact layer. Effective and practical countermeasures were devised and implemented. Device lifetime against the three different failure mechanisms was improved in every case by at least one order of magnitude.

Abstract: We demonstrate a novel power Si/4H-SiC heterojunction tunneling transistor (HETT) on the basis of theoretical analysis and experimental results. The HETT is an insulated gate drive device and has a unique switching mechanism. In the off-state, the heterojunction barrier prevents current flow between the Si source region and the 4H-SiC drift region. In the on-state, the width of the heterojunction barrier is controlled by the gate bias to allow tunneling current to flow. The HETT has a zero channel length structure that is more independent of channel mobility compared with a conventional 4H-SiC MOSFET. As a result, the HETT is expected to have low on-resistance. A HETT was fabricated with n+-type polycrystalline silicon on an n--type 4H-SiC epitaxial wafer for power devices. The fabricated HETT shows a low specific on-resistance of 6.8 m
cm2 (at Jd=500 A/cm2).

Abstract: We demonstrate a new high-voltage p+ Si/n- 4H-SiC heterojunction diode (HJD) by numerical simulation and experimental results. This HJD is expected to display good reverse recovery because of unipolar action similar to that of a SiC Schottky barrier diode (SBD) when forward biased. The blocking voltage of the HJD is almost equal to the ideal level in the drift region of n- 4H-SiC. In addition, the HJD has the potential for a lower reverse leakage current compared with the SBD. A HJD was fabricated with p+-type polycrystalline silicon on an n--type epitaxial layer of 4H-SiC. Measured reverse blocking voltage was 1600 V with low leakage current. Switching characteristics of the fabricated HJD showed nearly zero reverse recovery with an inductive load circuit.

Abstract: Thin (~10nm) Si layers have been deposited using Rapid Thermal CVD at temperatures ranging 950°C-1050°C. RTCVD deposited Si layers have been oxidized using N2O at 1300°C during relatively short times (15min) to produce SiO2 layers of 20-30nm. The interfacial characteristics of N2O oxidized RTCVD layers have been studied using the conductance method, showing a reduced traps density and a low band bending fluctuation when compared with conventional N2O grown oxides on 4H-SiC substrates. The surface topology of these layers has also been analyzed evidencing an adequate topography with low roughness.